RTL jobs in Sunnyvale, CA

Sunnyvale, California

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6d ago

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field5 10 years of experience in RTL design and microarchitectureStrong expertise in RTL design using SystemVerilog/VerilogMicroarchitecture development for complex digital systemsPerformance optimization and pipelining techniquesExperience with simulation and debugging tools such as:Synopsys VCS / Cadence XceliumFamiliarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler)Strong unde

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Contract, Third Party

Depends on Experience

ASIC/RTL Design Engineer

San Jose, California

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11d ago

Job Description: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro

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Third Party, Contract

Depends on Experience

CPU RTL Methodology Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are seeking a highly skilled and versatile engineer who thrives at the intersection of RTL design and CAD automation. This role is ideal for someone who understands RTL workflows deeply and can build scalable automation solutions to streamline design and debug processes. You'll work closely with CPU design teams to support RTL development, triage issues, and enhance prod

Full-time

USD 198,700.00 - 298,100.00 per year

RISCV CPU Systems Architecture/RTL Engineer - Senior Level

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low-power devices. In this role, you will contribute to architecture and product definition and be responsible for microarchitecture and RTL execution of CPU system features. These include, but are not limited to: System architecture - configuration access protocols and ordering requi

Full-time

USD 198,700.00 - 298,100.00 per year

ASIC Physical Design Engineer / RTL Synthesis Engineer

Remote

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Today

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Hiring: Senior ASIC RTL-to-Physical Design (RTL2PD) / RTL Synthesis Engineer Location: San Jose, CA(onsite) Experience: 8 to 12 years What will Be Doing: RTL Synthesis, Constraint writing, validation, Static timing AnalysisWriting Scripts/Modiying scripts for RTL synthesis, SDC creation, STADebug synthesi

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Third Party, Contract

$60 - $65

Design Engineer III

Sunnyvale, California

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Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

ASIC Design Hardware Engineer - SDC/STA - San Jose, CA (Hybrid)

Hybrid in San Jose, California

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4d ago

ASIC Design Hardware Engineer - SDC/STA (Hybrid) Location: San Jose, California, United States of America You are a diligent Design / SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and fu

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Third Party, Contract

$70+

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

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11d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

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Contract

90 - 130

Principal Design Engineer – Memory Controller-(CHI-G / DFI)

San Jose, California

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Today

Hi, Hope you are doing well. We do have below position. If interested, kindly repond. Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San JoseDuration would be 6 months to start and can be extended to 18 months. OnsiteDepartment: Hardware / SoC DesignLevel: Senior (8+ years) Role Summary We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub I

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Contract, Third Party

70+

Hardware Emulation

San Jose, California

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6d ago

Job Title: Senior Emulation EngineerExp:10+ years Location: San Jose, CA Duration: Long Term Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-

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Contract

55 - 75

Design Verification Engineer

San Jose, California

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5d ago

Position: Design Verification Engineer Type/Duration: Full time//Permanent Location: San Jose, CA (5 Days onsite in a week) Summary: We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments. Key Responsibilities: Develop and maintain UVM-based verification environments Create test plans, testcases, and coverage models Perform functional verification of RTL designs Debug RTL and testbench issues Driv

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Full-time, Third Party

Depends on Experience

Design Engineer

Sunnyvale, California

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10d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

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Third Party, Contract

$82 - $85

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

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19d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

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Contract, Third Party

Depends on Experience

Physical Design Engineer & DV Engineers

Sunnyvale, California

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21d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Senior Emulation Engineer

San Jose, California

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Today

We have an open Emulation Engineer position in San Jose, USA. Senior Emulation Engineer Location: San Jose, CA Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software br

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Third Party, Contract

Depends on Experience

Senior CPU RTL Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for CPU RTL development targeted for high performance, low power devices. Works with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life cycle. Responsible for performance exploration; explores

Full-time

USD 142,200.00 - 213,400.00 per year

CPU RTL LLC Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This i

Full-time

USD 198,700.00 - 298,100.00 per year

Principal Digital RTL Engineer

San Jose, California

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Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 185,000.00 - 240,000.00 per year

Senior RTL Engineer, Memory Centric Computing

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 138,000.00 - 206,000.00 per year

Lead RTL/FPGA Design Engineer

Remote

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Today

About Aalyria: Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any har

Full-time

USD 170,000.00 - 195,000.00 per year

RTL jobs in Sunnyvale, CA, USA