Static Timing Analysis jobs in California

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

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Yesterday

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

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Full-time

Depends on Experience

SoC Static Timing Analysis (STA) Engineer, HBM

Folsom, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern d

Full-time

USD 198,000.00 - 337,000.00 per year

Physical Design Engineer – Lead

San Jose, California

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14d ago

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

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Full-time

Depends on Experience

Design For Test (DFT) Engineer

San Jose, California

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Yesterday

Role: Design For Test (DFT) Engineer Location: San Jose, CA (Onsite: M-F) Duration: 6 Months Contract Pay Rate: $100-130/hr W2 Description: Looking for a Design-for-Test contractor to test and validate the next generation chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. Job Responsibilities: Experience with memory BIST Siemens

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Contract

100 - 130

Physical Design Engineer

Palo Alto, California

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14d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

FE Engineer

Sunnyvale, California

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Today

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practice

Full-time

Physical Design Engineer with Cadence Innovus

San Jose, California

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Today

Conduct EM/IR analysis.Strong experience with Cadence Innovus.Expertise in the complete Physical Design cycle from RTL to Tape-out.Strong TCL and/or PERL scripting skills.Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.Perform timing closure using various methodologies and strategies, including top-level STA.Collaborate closely with IC Design and RTL Engineering teams.

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Full-time

Depends on Experience

Physical Design Engineer

California City, California

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Today

Job Title: Physical Design Engineer Employment Type: Full-Time (FTE) Locations: San Jose, CA / San Diego, CA / Irvine, CA Experience: 12+ Years Required Technical Skills Strong hands-on experience with Cadence Innovus. End-to-end Physical Design experience from RTL to tape-out. RTL synthesis and Static Timing Analysis (STA). Timing closure, including top-level STA. Place & Route (P&R), Clock Tree Synthesis (CTS), and clock-tree optimization. Floorplanning and physical layout. Physical veri

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Full-time

Depends on Experience

Physical Design Engineer GPU / High-Performance SoC

Remote

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Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

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Contract

$60 - $80

Design For Test (DFT) Engineer

San Jose, California

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Today

Job Description Onsite San Jose - 5 days a week Description The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. JOB RESPONSIBILITIES: Experience with memory BIST - Siemens Tessent Flow Experience with gate-level simulation and si

Contract

Senior Principal Software Engineer

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geogra

Full-time

USD 161,000.00 - 299,000.00 per year

Senior Software Architect

San Jose, California

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Today

Full-time

USD 210,000.00 - 390,000.00 per year

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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Today

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

CPU Server FV/CLP/STA engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/op

Full-time

USD 147,900.00 - 221,900.00 per year

Full Chip Timing Modeling and Integration Engineer

San Jose, California

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Today

Job Details: Job Description: About the Role Altera is seeking highly qualified candidates to join our Full Chip Timing team. Altera continues to deliver industry-leading Field-Programmable Gate Array (FPGA) solutions to customers. As a Full Chip Timing Modeling and Integration Engineer, you will develop timing methodologies and execute full-chip timing for Altera's next-generation product lines using the world's most advanced process technologies. This is a fast-paced, dynamic environment

Full-time

USD 133,200.00 - 192,825.00 per year

Senior Principal Engineer

Remote or San Jose, California

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Today

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies

Full-time

USD 231,500.00 - 304,500.00 per year

CPU Server Floorplan and Integration Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work! Our Mission We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joini

Full-time

USD 147,900.00 - 221,900.00 per year

Principal Engineer, SOC Design

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 219,000.00 - 351,000.00 per year

CPU STA CAD Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. As CPU STA CAD engineer, you will build and su

Full-time

USD 209,300.00 - 313,900.00 per year

Principal CPU PPA Pathfinding Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: Define competitive PPA options that will shape Qualcomm's future CPU products. Role Overview As a Principal CPU PPA Pathfinding Engineer, you will analyze, define, and evaluate power, performance, and area options for future Qualcomm CPU projects. You will combine deep CPU implementation expertise with competitive analysis to translate architectural concepts, competitor and i

Full-time

USD 216,600.00 - 325,000.00 per year

Static Timing Analysis jobs in California, USA