SystemVerilog jobs in Tempe, AZ

Senior Systems and Test Integration Engineer

Scottsdale, Arizona

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Today

M9 Solutions is dedicated to providing IT services and solutions to the Federal Government by mobilizing the right people, skills, clearance levels, and technologies to help organizations that desire improved performance and modern, sustainable change. M9 has provided quality IT services and support to more than 30 Federal Agencies and multiple commercial customers nationwide. Our capabilities include IT Talent Solutions, Data Delivery & Analytics, Cyber Security, Cloud Migration, Applications a

Full-time

USD 115,000.00 - 130,000.00 per year

Hardware/FPGA Engineer

Tempe, Arizona

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Today

About us One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do As a Hardware Design Engineer, you will support the end-to-

Full-time

USD 132,500.00 - 209,500.00 per year

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

Scottsdale, Arizona

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Today

Basic Qualifications Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified

Full-time

USD 135,396.00 - 150,205.00 per year

Principal Digital Verification Engineer

Chandler, Arizona

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Today

Job Title: Principal Digital Verification Engineer Primary Location: Chandler, Arizona, USA Role Summary: The Advanced Power Systems group within NXP's Power and Energy Business Line is seeking a Senior Digital Verification Engineer to develop next-generation Power Management ICs (PMICs) for automotive and industrial applications. This role will lead digital verification from architecture review through verification signoff, ensuring functionality, quality, reliability, and compliance. Job Re

Full-time

Hardware Design Engineer

Tempe, Arizona

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Today

Full-time

USD 132,500.00 - 209,500.00 per year

Principal Analog Mixed Signal Verification Engineer

Chandler, Arizona

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Today

Job Title: Principal Analog Mixed-Signal Verification Engineer Primary Location: Chandler, Arizona, USA Role Summary: Lead analog and mixed-signal verification for automotive and industrial PMIC products from specification through verification signoff.Define verification strategies, environments, regressions, and coverage objectives for complex mixed-signal IPs, subsystems, and SoCs.Collaborate with cross-functional teams to ensure product quality, reliability, functional correctness, safety,

Full-time

Principal Engineer

Chandler, Arizona

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Today

Job Description: Duties: Perform semiconductor engineering design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry. Participate in the digital functional verification of NXP's mixed-signal circuit designs. Responsible for developing the UVM simulation environment (drivers, monitors, checkers, and assertions) and bridge with mixed signal verification. Develop and run digital and top-level simulations accordi

Full-time

USD 174,070.00 per year

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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3d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

Advanced ASIC FPGA Design Engineer

Scottsdale, Arizona

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Today

Full-time

USD 135,396.00 - 150,205.00 per year

Design Verification Engineer

Remote

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Yesterday

Job SummaryWe are seeking a motivated Design Verification Engineer with 13 years of experience in digital design verification and semiconductor engineering. The candidate will work with RTL design and verification teams to develop testbenches, execute simulation-based verification, debug design issues, and validate the functionality and reliability of digital designs. The ideal candidate should have hands-on knowledge of Verilog, SystemVerilog, digital logic design, and verification methodologie

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Full-time

75000 - 100,000

SoC / RTL Integration Engineer

Remote

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Today

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Job Title : SoC / RTL Integration Engineer Location : Remote Good in understanding RTL Design and Digital concepts Subsystem or SoC integration Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc. SS integration using Verilog/system Verilog, synthesis, timing constraints,

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Contract

70 - 75

SOC/IP Integration Engineer (eInfochips Inc)

Remote or California

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Today

Position: SOC/IP Integration Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Good in understanding RTL Design and Digital conceptsSubsystem or SoC integrationIntegration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration.Ensure customer satisfaction

Full-time

Senior FPGA Prototyping Engineer

Remote

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Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price - and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missi

Full-time

USD 120,000.00 - 225,000.00 per year

Field Applications Engineer (FAE)

Remote or Maryland

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Today

Job Details: Job Description: For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries. Join us in our journey to becoming the #1 FPGA company! What You Will Do As a Field Applications Engineer (FAE), your key responsibilities will be: Driving FPGA Adoption: Identify, influence, and enable the adoption of Altera FPGA-based solutions at key

Full-time

USD 134,800.00 - 195,100.00 per year

Principal FPGA Engineer

Remote or Danbury, Connecticut

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Today

Job Title: Principal FPGA Engineer Department: Product Development Reports to: Director of Hardware Engineering Office: Danbury, CT Work Location: Remote (for those in Eastern or Central time zones) Owl Cyber Defense is a leader and trusted partner in cyber security. We deliver solutions that protect and connect the world's most critical networks. Owl's product lines of cross domain, data diode, and portable media solutions provide the strongest available security checkpoints for threat preven

Full-time

USD 160,000.00 - 210,000.00 per year

Senior DfT Engineer

Chandler, Arizona

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Today

As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be: 1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product Engineer, Quality Engineer, Validation Engineer - to identify the superset of requirements for Testability of the chip (Functional mode, Debug mode, ATPG). 2) Gain deep understanding on existing and innovative ways to insert DfT for complex analog and mixed-signal IPs, standard Macros (RAM, ROM, N

Full-time

FPGA Engineer (Space)

Tempe, Arizona

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Today

About us One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do As a FPGA Engineer on the Space Infrastructure team, you wi

Full-time

USD 117,000.00 - 185,000.00 per year

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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10d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

Easy Apply

Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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9d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

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Contract

Depends on Experience

DFT MBIST Staff Engineer

Remote

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9d ago

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

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Third Party, Contract

90 - 100

SystemVerilog jobs in Tempe, AZ, USA