UVM jobs in Santa Clara, CA

Sunnyvale, California

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5d ago

Hello, Hope you are doing well. Title: ARM IP Verification Engineer Location: Sunnyvale, CA Are you passionate about building robust verification environments for next-gen silicon? We are looking for an experienced ARM IP-Level Verification Engineer to join our team in Sunnyvale, CA. If you thrive on architecting complex UVM testbenches, driving coverage closure, and developing custom VIP from the ground up, we want to hear from you. Key Focus Areas: SystemVerilog & UVM mastery Custom VIP de

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Contract

50 - 60

SoC Verification Engineer - NoC / UVM

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

Design Verification Engineer

San Jose, California

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4d ago

Position: Design Verification Engineer Type/Duration: Full time//Permanent Location: San Jose, CA (5 Days onsite in a week) Summary: We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments. Key Responsibilities: Develop and maintain UVM-based verification environments Create test plans, testcases, and coverage models Perform functional verification of RTL designs Debug RTL and testbench issues Driv

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Full-time, Third Party

Depends on Experience

SoC Design Verification Engineer

San Jose, California

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3d ago

Position Title: SoC Design Verification Engineer Location: San Jose, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute S

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Full-time, Third Party

Depends on Experience

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

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Yesterday

Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ Years Job Type: Contract / Long-Term Job Summary We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP. The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure,

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Full-time, Part-time, Third Party, Contract

Senior Emulation/Verification Engineer In Bay Area, CA || Hybrid Role

Hybrid in Menlo Park, California

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Today

Role: Senior Emulation/Verification EngineerDuration: Long TermLocation: Bay Area, CA || Hybrid Role Job Description-: We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

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Contract

Depends on Experience

Design Verification Engineer

San Jose, California

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19d ago

Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required 8+ years of Design Verification experience in s

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Contract

Depends on Experience

Design Engineer

Sunnyvale, California

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9d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

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Third Party, Contract

$82 - $85

ASIC Emulation Engineer

San Jose, California

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19d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

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Contract

60 - 75

Design Verification Engineer (Only W2)

Santa Clara, California

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Today

Job descriptionYour Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers'' specifications whether they''re a major telecom organization or automotive company, etc. What You Can Expect As a leading member of the Network S

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Full-time

150,000 - 300000

Senior Emulation Engineer

San Jose, California

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Today

We have an open Emulation Engineer position in San Jose, USA. Senior Emulation Engineer Location: San Jose, CA Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software br

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Third Party, Contract

Depends on Experience

Design Engineer III

Sunnyvale, California

•

Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

ASIC Verification Engineer

San Jose, California

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Today

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our d

Full-time

Core Engineering - Design Engineer III

Sunnyvale, California

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Today

Job#: 3045115 Job Description: Core Engineering - Design Engineer Location: Sunnyvale, California (Partial Remote) 3 days / week onsite Compensation: $70- $80 Hourly Role Overview This position is for a Design Verification engineer focused on wearables silicon accelerator IPs. The role involves testbench development, coverage-driven verification, RTL debug, and power and performance measurement. The successful candidate will work with a small team to build and run testbenches, analyze cove

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Full-time

$70 - $80 per hour

Senior ASIC Verification Engineer (PCIe/CXL)

San Jose, California

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing

Full-time

USD 145,600.00 per year

Senior Staff Engineer, GPU Design Verification (Subsystems)

San Jose, California

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Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 180,200.00 - 297,200.00 per year

AI/ML Silicon Verification Solutions Engineer - Tools

San Jose, California

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Today

Full-time

USD 145,600.00 per year

Senior Staff Engineer, GPU Design Verification (Formal Verification)

San Jose, California

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Today

Full-time

USD 198,200.00 - 297,200.00 per year

Principal Engineer, Design Verification - DDR Memory Subsystems

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, edge computing, and embedded systems. About the Role

Full-time

USD 209,500.00 - 299,200.00 per year

ASIC Verification Engineer

San Jose, California

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Today

Company Description Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world's most critical infrastructure-from data centers to next generation cloud and AI platforms-by secur

Full-time

UVM jobs in Santa Clara, CA, USA