Atpg jobs | Dice.com

Austin, Texas

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 80,500.00 per year

Sr DFT/ATPG Engineer-Mixed-Signal IP

Fort Collins, Colorado

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Today

Full-time

USD 175,000.00 per year

DFT Engineer in San Jose, CA (Hybrid role)

Hybrid in San Jose, California

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Yesterday

Role: DFT Engineer Location: San Jose, CA (Hybrid role) Duration: 12+ months Job description: Good understanding of DFT fundamentals and methodologyExperience with DFT insertion and verificationExperience with Tessent tools:Tessent Streaming Scan Network Op SWTessent Memory BIST-NS Ap SWTessent Memory BIST-NS repair Op SWTessent Test Kompress Ap SWTessent IJTAG Ap SWTessent Scan Pro Ap SWAbility to work under pressure and debug issues promptly

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Contract, Third Party

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

Design For Test (DFT) Engineer

San Jose, California

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Yesterday

Role: Design For Test (DFT) Engineer Location: San Jose, CA (Onsite: M-F) Duration: 6 Months Contract Pay Rate: $100-130/hr W2 Description: Looking for a Design-for-Test contractor to test and validate the next generation chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. Job Responsibilities: Experience with memory BIST Siemens

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Contract

100 - 130

DFT (Design for Test) Lead

Remote

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21d ago

Job Title: DFT (Design for Test) Lead Location: (Remote) Shift: 9am 5pm PST Duration: 12+ Months Contract Role on W2 Job Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability f

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Contract

75 - 80

Senior SoC Validation Engineer

San Jose, California

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Today

We are looking for Senior SoC Validation Engineer for our client in San Jose, CAJob Title: Senior SoC Validation Engineer Job Location: San Jose, CA Job Type: Contract Pay Range: $72.35hr - $76.36hr Job Overview: We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces. This role centers on ATE program development, DFT/BIST enablement, yield/quality optimization, and high-volume manufacturability. Strong un

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Contract, Third Party

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

DFT MBIST Staff Engineer

Remote

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8d ago

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

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Contract, Third Party

90 - 100

Validation Engineer 3 # 26-26845

San Jose, California

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Today

Duration: 12-month contract Job Description:We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces.This role centers on ATE program development, DFT/BIST enablement, yield/quality optimization, and high-volume manufacturability.Strong understanding of SerDes and protocols such as UCIe and PCIe is required, with emphasis on translating characterization into robust, multisite production tests.Experience wi

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Contract

$75 - $85

CPU Gate Level Synthesis Engineer

Santa Clara, California

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Today

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our p

Full-time

Design For Test (DFT) Engineer

San Jose, California

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Today

Job Description Onsite San Jose - 5 days a week Description The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. JOB RESPONSIBILITIES: Experience with memory BIST - Siemens Tessent Flow Experience with gate-level simulation and si

Contract

Senior DFT Engineer

Santa Clara, California

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Today

Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital de

Full-time

USD130000.0/ANNUAL - USD150000.0/ANNUAL

Test Engineer-Various Levels

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire exceptional Test Engineers to join our Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per wee

Full-time

USD 126,000.00 - 234,000.00 per year

SR ENGINEER, HIG HBM SOC VERIFICATION

Richardson, Texas

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Develop test plans at SOC Level and analyze Coverage. Build verification environments to verify complex SOCs. Develop Random/Directed test in RTL and GLS environments. Review architectural specific

Full-time

Product Engineering Manager

Austin, Texas

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing

Full-time

USD 128,800.00 per year

CPU Core Staff DFT Engineer

Santa Clara, California

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Today

Full-time

USD 175,000.00 per year

DFT Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's Core Switching Group division is seeking a candidate for a DFT engineer. Products include networking switches for Scale up and Scale Out for traditional and AI data centers. This position is at our R&D center in San Jose, CA. The successful

Full-time

USD 121,900.00 - 195,000.00 per year

Senior Software Engineer

Fort Meade, Maryland

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Today

Belay Technologies has been voted Baltimore Business Journal's (BBJ) Best Places to Work 2026! Belay Technologies is seeking a Senior Software Engineer to join our intel team. You will be supporting TAO and working alongside the ATPG customer to build and maintain tools that support the operational mission. You will be working as part of a team that identifies and provides solutions to resolve workflow inefficiencies and take advantage of opportunities to advance mission. Day to day, you will di

Full-time

USD 190,000.00 - 240,000.00 per year

DFT Design Engineer, Machine Learning Acceleration

Austin, Texas

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Today

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you\'ll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems?our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We\'re looking for an ASIC D

Full-time