Dft jobs in california

Principal DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 220,000.00 - 355,000.00 per year

Principal DFT Engineer (Silicon Engineering)

Irvine, California

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Today

Full-time

USD 210,000.00 - 340,000.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

ASIC DFT Staff Engineer

Remote

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Today

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

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Third Party, Contract

Design for Test (DFT) Engineer

Hybrid in Santa Clara, California

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13d ago

Title: Design for Test (DFT) Engineer Location: Hybrid (Travel to Santa Clara) Duration: 1year Key Skills & Experience 3+ years of experience working as a DFT Engineer.Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improv

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Contract

Depends on Experience

Senior DFT Engineer

Santa Clara, California

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Today

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multic

Full-time

USD 196,000.00 - 310,500.00 per year

DFT Engineer

Mountain View, California

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5d ago

Hi, Job Title : DFT Engineer (Scan / MBIST / ATPG) Location: Mountain View CA DFT Engineer (Scan / MBIST / ATPG) We are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs. Thanks and Regards, Praveenkumar

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Full-time, Third Party

Depends on Experience

Sr. ASIC DFT Engineer (Silicon)

Irvine, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 165,000.00 - 260,000.00 per year

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 175,000.00 - 280,000.00 per year

CPU DFT Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to

Full-time

USD 142,200.00 - 213,400.00 per year

DFT Engineer

San Jose, California

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Today

Position : DFT Engineer Location : Austin,TX / San Jose,CA Duration : Long-term contract The Role We are seeking highly skilled and motivated Senior/Staff DFT (Design for Test) Engineers with a strong focus on high-performance digital design to take end-to-end ownership of robust, testable silicon, from early test strategy definition to verified DFT implementation, pattern generation, and silicon bring-up. You will join a multidisciplinary group creating next-generation accelerators where digita

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Contract, Third Party

Depends on Experience

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

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19d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

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Contract, Third Party

Depends on Experience

DFT Engineers

Santa Clara, California

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3d ago

Position Title: DFT Engineers Location: Santa Clara, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and MBIST MBIST Repair Implementation and Verification Generating collaterals for Test Timing and Place and Route Expertise in IJTAG 1687 standard and good at understanding ICL and PDL standard Spec Verification of DFT features including Boundary Scan JTAG SCAN MBIST High Speed IO

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Full-time, Third Party

Depends on Experience

DFT Engineer

Santa Clara, California

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6d ago

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Required Skills & Qualifications 4+ years of hands-on experience in DFT and ATPGfor SoC or ASIC designsStrong understanding of DFT fundamentalsincluding controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Tes

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Contract

Depends on Experience

Lead ASIC DFT Engineer

Remote

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21d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

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Third Party, Contract

110 - 120

DFT (Design For Test) Lead

Remote

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6d ago

Job Title: DFT (Design For Test) Lead Looking for how many contractors to fill this role?: 2 Duration: 7/27/2026 to 9/30/2027 (possibly extending longer based on project timelines) Location? US Remote Requirement: Candidate should be available to work California times, 9-5 PST**) Rounds of interview? 1st interview is phone screen, 2nd interview is with 2-3 engineers on team ASIC DFT experienced consulting engineers, lead-calibre. This project revision will at least go until September 2027

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Third Party, Contract

Depends on Experience

DFT Engineer

Hybrid in San Jose, California

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6d ago

Principal DFT Engineer-San Jose,CA We are hiring for a Principal DFT Engineer with strong Siemens Tessent experience for onsite opportunity in San Jose, CA. Key DFT Responsibilities & Skills: Tool Expertise: Extensive experience with the Siemens Tessent tool suite.DFT Architecture & Integration: Responsible for top-level DFT planning and integration.ATPG & ATE: Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure

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Contract

Depends on Experience

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

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10d ago

Hi, Hope you are doing well. We have the position below.Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location: San Jose, CA Duration would be 6 months to start and can be extended to 18 months. Onsite Experience: Lead Verification Engineer: 10+ years Position Summary We are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transcation Layer, Controller, PHY and Serdes. The candidate will be responsible for v

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Contract

60+

Design Verification Engineer

Remote

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5d ago

Hi - Full Time Role Job Title: Design Verification Engineer -Performance Modelling Location : Remote USA Strong understanding of SV and UVM and good debugging skills.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely wi

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Full-time

Depends on Experience

Senior Electrical Engineer

Hybrid in Palo Alto, California

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2d ago

Senior Electric Engineer Youll own the electrical engineering team for a breakthrough stealth-stage neurotechnology and brain-computer interface (BCI) startup building an AI-powered neural interface platform. In this role, you will own the wearable electrical architecture from schematic through production, helping bring a highly integrated next-generation device to market. The platform combines cameras, spatial audio microphones, EEG sensors, Wi-Fi/BLE connectivity, and advanced power managemen

Easy Apply

Full-time

225000 - 250000

Dft jobs in California, USA