Dft jobs in california

Engineering Intern - ASIC DFT (Spring 2027 Co-Op)

Palo Alto, California

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Today

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what's possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it

Full-time

USD 45.00 - 51.00 per hour

ASIC DFT Engineer

Palo Alto, California

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Today

Full-time

Compensation information provided in the description

Senior DFT Engineer

Santa Clara, California

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Today

Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital de

Full-time

USD130000.0/ANNUAL - USD150000.0/ANNUAL

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Principal DFT Engineer (Silicon Engineering)

Irvine, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 210,000.00 - 340,000.00 per year

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Principal DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 220,000.00 - 355,000.00 per year

DFT MBIST Staff Engineer

Remote

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Today

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Design For Test (DFT) Engineer

San Jose, California

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Today

Job Description Onsite San Jose - 5 days a week Description The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. JOB RESPONSIBILITIES: Experience with memory BIST - Siemens Tessent Flow Experience with gate-level simulation and si

Contract

DFT Engineer

Santa Clara, California

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Today

We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality. Key Responsibilities Create and execute test plans for DFX features including Scan, MBIST, SSN, EDT, IJTAG, and JTAG. Verify DFX implementations at I

Easy Apply

Contract

Depends on Experience

DFT (Design for Test) Engineer (California, Texas) - W2 Only

San Jose, California

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Yesterday

Hello, Hope you are doing good ! Please find the JD below and share your updated resume POSITION: DFT (Design For Test) Engineer Location: San Jose, CA and Austin, TX Requirements: Good understanding of DFT fundamentals and methodology Experience with DFT insertion and verification Experience with Tessent tools Tessent Streaming Scan Network Op SW Tessent MemoryBIST-NS Ap SW Tessent MemoryBIST-NS repair Op SW Tessent TestKompress Ap SW Tessent IJTAG Ap SW Tessent ScanPro Ap SW Ability to work

Easy Apply

Full-time

$60 - $70

DFT Engineers - Santa Clara, CA

Santa Clara, California

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30+d ago

Job Title: DFT Engineers Location: Santa Clara, CA Job Description: 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock ve

Easy Apply

Contract

Depends on Experience

DFT Engineer

California

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Today

Job Title: DFT Engineer Location: Saratoga, CA (Onsite) Duration: Contract & Full-Time Job Description: Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG). Proficiency in Synthesis design constraints. ( Ie SDC) Prior experience with Serializers/Deserilizers. Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis, Define and implement OCC. Exposure to

Easy Apply

Full-time

DFX/DFT Engineer

Santa Clara, California

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Today

DFX/DFT Engineer Location : Bay area CA Experience :- 6 to 8 yrs Onsite 6-12 months JD:- We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality. Key Responsibilities Create and execute test plans for DF

Easy Apply

Contract

Depends on Experience

DFT Engineers

Santa Clara, California

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28d ago

5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals including controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Test methodologies for interface and pin level validationSolid understanding of clock DFT and clock verification conceptsStrong grasp of digital design and RTL fundamenta

Easy Apply

Contract

Depends on Experience

DFT Engineer

Santa Clara, California

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21d ago

Job title: DFT Engineer Location: Santa Clara, California 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock ve

Easy Apply

Contract

DFT Engineer in San Jose, CA (Hybrid role)

Hybrid in San Jose, California

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Yesterday

Role: DFT Engineer Location: San Jose, CA (Hybrid role) Duration: 12+ months Job description: Good understanding of DFT fundamentals and methodologyExperience with DFT insertion and verificationExperience with Tessent tools:Tessent Streaming Scan Network Op SWTessent Memory BIST-NS Ap SWTessent Memory BIST-NS repair Op SWTessent Test Kompress Ap SWTessent IJTAG Ap SWTessent Scan Pro Ap SWAbility to work under pressure and debug issues promptly

Easy Apply

Contract, Third Party

Depends on Experience

PCB Layout Engineer

Menlo Park, California

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Today

Job Description: Must have : Allegro PCB and CAD Software Key Responsibilities Own end-to-end PCB layout for complex, high-density designs used in data center server boardsPerform high-speed digital layout for interfaces like HBM,DDR4/5, PCIe Gen 5/6, USB 3.2 or higher, with attention to controlled impedance, length matching, and crosstalk mitigationDevelop and enforce layout design rules for High-speed digital, analog, mixed-signal, and power domains within tightly constrained wearable form fac

Easy Apply

Contract

Depends on Experience

Design For Test (DFT) Engineer

San Jose, California

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Yesterday

Role: Design For Test (DFT) Engineer Location: San Jose, CA (Onsite: M-F) Duration: 6 Months Contract Pay Rate: $100-130/hr W2 Description: Looking for a Design-for-Test contractor to test and validate the next generation chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. Job Responsibilities: Experience with memory BIST Siemens

Easy Apply

Contract

100 - 130

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

Easy Apply

Third Party, Contract

90 - 100

Dft jobs in California, USA