Verilog jobs in cupertino, ca

San Jose, California

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4d ago

Position Title: SoC Design Verification Engineer Location: San Jose, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute S

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Full-time, Third Party

Depends on Experience

Principal Design Engineer – Memory Controller-(CHI-G / DFI)

San Jose, California

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Today

Hi, Hope you are doing well. We do have below position. If interested, kindly repond. Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San JoseDuration would be 6 months to start and can be extended to 18 months. OnsiteDepartment: Hardware / SoC DesignLevel: Senior (8+ years) Role Summary We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub I

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Contract, Third Party

70+

ASIC Emulation Engineer

San Jose, California

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20d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

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Contract

60 - 75

Senior Staff CPU Backend Design Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: This individual leads the team to improve engineering efficiency, product quality and responsibility of working with microarchitecture and RTL design team to implement the designs, meeting aggressive power, area and performance goals using industry standard tools/flows. Works with CPU microarchitecture team to understand specifications and design trade-offs in pipeline and st

Full-time

USD 216,091.00 - 298,100.00 per year

Senior Firmware Engineer

Cupertino, California

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Today

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and extraordinarily hardworking FW Design Engineer. As a member of our multifaceted group, you will have the outstanding and great opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Description In this job you

Full-time

Senior Emulation Engineer

San Jose, California

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Today

We have an open Emulation Engineer position in San Jose, USA. Senior Emulation Engineer Location: San Jose, CA Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software br

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Third Party, Contract

Depends on Experience

Lead Functional Product Engineer, Power Analysis

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments. Key Responsibilities Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages Reproduce, debug, and resolve customer-reported issues in power an

Full-time

USD 114,800.00 - 213,200.00 per year

Silicon Prototyping Engineer

Cupertino, California

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Today

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practice

Full-time

ASIC Design Hardware Engineer - SDC/STA - San Jose, CA (Hybrid)

Hybrid in San Jose, California

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4d ago

ASIC Design Hardware Engineer - SDC/STA (Hybrid) Location: San Jose, California, United States of America You are a diligent Design / SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and fu

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Third Party, Contract

$70+

CPU RTL LLC Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This i

Full-time

USD 198,700.00 - 298,100.00 per year

TFT Process Engineer

Cupertino, California

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Today

Apple is looking for world-class Thin Film Transistor (TFT) panel process engineer who will be an integral part of next Apple products. TFT process team is responsible for delivering advanced TFT panel technologies and architectures to realize world's best performance in iPad and Mac displays. Seeking individual will serve as a focal point in overseeing the unit process and integration of TFT architecture; from research, development to mass production implementation of TFT panels. This includes

Full-time

Sr. Staff Engineer, Optical Link Design

San Jose, California

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Today

Sr. Staff Engineer, Optical Link Design Location: San Jose, CA (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem,

Full-time

USD 175,000.00 - 223,000.00 per year

Principal Product Engineer, Synthesis

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Seeking a highly motivated engineer who can drive improvement to Cadence's synthesis and place & route products from a design perspective. The position provides an excellent opportunity to work closely with the R&D team to define the roadmap of the products. Job responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for

Full-time

USD 136,500.00 - 253,500.00 per year

Summer 2027 Masters Field Applications Engineer Intern

San Jose, California

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 104,000.00 per year

DFT Engineer

Santa Clara, California

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Today

Benefits: Day-1 Onsite Competitive salary Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite) Employment Type: Long-Term Contract Interview Process: Virtual Interviews Compensation: Based on Experience (DOE) Engagement: ANY Preference: Local candidates or those able to work onsite We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team. In this role, you will be responsible for designing and implementing De

Full-time

Compensation information provided in the description

Sr. Staff Engineer, Electrical Link Architecture

San Jose, California

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Today

Sr. Staff Engineer, Electrical Link Architecture Location: San Jose, CA (on-site) Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co-packaged optics (CPO), we develop silicon photonics solutions that deliver unprecedented bandwidth density and reach, at a fraction of the power consumption required to scale next-generation AI models. Backed by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with

Full-time

USD 190,000.00 - 223,000.00 per year

Firmware/Software Tech Lead

San Jose, California

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Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 160,000.00 - 200,000.00 per year

Graduate - Senior Engineer Digital IC Design

San Jose, California

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Today

This opening is part of Infineon's Graduate program. The Graduate Program gives new Graduates the opportunity to gain enriching and diverse experiences and work side by side with experienced leaders to power your career. In your new role you will: Design and implement digital circuits for automotive electronic applicationDevelop digital architectures that meet automotive industry standards for reliability, safety, and performance.Write and optimize low power Register Transfer Level (RTL) code,

Full-time

Senior RTL Engineer, Memory Centric Computing

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 138,000.00 - 206,000.00 per year

RISCV CPU Systems Architecture/RTL Engineer - Senior Level

Santa Clara, California

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Yesterday

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low-power devices. In this role, you will contribute to architecture and product definition and be responsible for microarchitecture and RTL execution of CPU system features. These include, but are not limited to: System architecture - configuration access protocols and ordering requi

Full-time

USD 198,700.00 - 298,100.00 per year

Verilog jobs in Cupertino, CA, USA