Zebu jobs in california

Senior Emulation/Verification Engineer In Bay Area, CA || Hybrid Role

Hybrid in Menlo Park, California

•

Today

Role: Senior Emulation/Verification EngineerDuration: Long TermLocation: Bay Area, CA || Hybrid Role Job Description-: We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

Easy Apply

Contract

Depends on Experience

Sr. Emulation Engineer

San Jose, California

•

11d ago

Job Title: Sr. Emulation Engineer Location: San Jose, CA (Onsite) Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platformsAdapt SoC designs for Emulation and PrototypingDevelop and debug emulation testbenches and system-level environmentsSupport pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and valid

Easy Apply

Third Party, Contract

Depends on Experience

Emulation Engineer

Remote or California

•

Yesterday

Senior Emulation Engineer Location: San Jose, CA (Remote) Experience: 10+ Years We are hiring an experienced Senior Emulation Engineer with strong expertise in Siemens Veloce, Cadence Palladium, or Synopsys ZeBu. Required Skills: Hands-on experience with Veloce, Palladium, or ZeBu emulation platforms Experience with FPGA prototyping (HAPS, Protium, or proFPGA) Strong knowledge of PCIe, UCIe, LPDDR, and HBM Solid understanding of SoC architecture, RTL (Verilog/SystemVerilog), and digital des

Easy Apply

Full-time, Part-time, Contract, Third Party

Hardware Emulation

San Jose, California

•

6d ago

Job Title: Senior Emulation EngineerExp:10+ years Location: San Jose, CA Duration: Long Term Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-

Easy Apply

Contract

55 - 75

ASIC Emulation Engineer

San Jose, California

•

19d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

Easy Apply

Contract

60 - 75

Senior Emulation Engineer

San Jose, California

•

Today

We have an open Emulation Engineer position in San Jose, USA. Senior Emulation Engineer Location: San Jose, CA Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software br

Easy Apply

Third Party, Contract

Depends on Experience

Design Engineer III

Sunnyvale, California

•

Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

•

Yesterday

Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ Years Job Type: Contract / Long-Term Job Summary We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP. The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure,

Easy Apply

Full-time, Part-time, Third Party, Contract

Emulation Verification Engineer

San Francisco, California

•

Today

Imagine what you could at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengt

Full-time

Post-Silicon Systems Software Validation Engineer

Remote or California

•

Today

Position: Post-Silicon Systems Software Validation Engineer Job Description: - Strong programming skills (Python, Lua, C/C++, Rust, Go, etc) - A solid understanding of computer architecture and chip/system validation methodologies - Firmware testing and/or development (BIOS, BMC, drivers) - Domain expertise in any of these areas: PCIe, HBM, GPUs, neural networks, ML HW architecture - Knowledge of the full validation lifecycle from RTL simulation (SystemVerilog/UVM, VCS, Questa, Xcelium) and emu

Full-time

USD 87,400.00 - 165,000.00 per year

Principal Engineer, Digital Verification and Emulation

San Jose, California

•

Today

Principal Engineer, Digital Verification & Emulation Location: San Jose, CA - on-site Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics, or CPO, we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry leaders including NVIDIA, AMD, MediaTek and Intel, and manufactured in partnership with the world's leading semi

Full-time

USD 190,000.00 - 250,000.00 per year

Design Engineer

Sunnyvale, California

•

10d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

Easy Apply

Third Party, Contract

$82 - $85

Design Verification Engineer III

Sunnyvale, California

•

Today

Job Title: Design Verification Engineer Location: Sunnyvale, CA (Onsite 3 days/week) Duration: Contract - 6 months, extension TBD Pay Range: $60/hr - $65.32/hr (W2). Job ID: 407927 About BCforward BCforward is a leading global IT consulting and workforce solutions firm providing services and support to Fortune 500 and government clients. Founded in 1998, BCforward has grown with our customers needs into a full-service business solutions provider. With delivery centers and offices across No

Easy Apply

Contract

$65.32 - $65.32 per hour

CPU Emulation Engineer

Santa Clara, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a CPU Emulation Engineer, you will work as part of CPU verification team to deliver emulation-based solutions for CPU team. You will work closely with all disciplines of CPU team to help verify and validate high performance CPUs. Role and Responsibilities Work closely with CPU RTL, performance, verification and SW teams to deliver emulation-based solutions.Architect and de

Full-time

USD 167,100.00 - 250,700.00 per year

Sr Staff COE Emulation Engineer

San Diego, California

•

Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 135,900.00 - 201,130.00 per year

Senior ASIC Emulation Engineer

Remote

•

Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep

Full-time

USD 170,000.00 - 250,000.00 per year

Core Engineering - Design Engineer III

Sunnyvale, California

•

Today

Job#: 3045115 Job Description: Core Engineering - Design Engineer Location: Sunnyvale, California (Partial Remote) 3 days / week onsite Compensation: $70- $80 Hourly Role Overview This position is for a Design Verification engineer focused on wearables silicon accelerator IPs. The role involves testbench development, coverage-driven verification, RTL debug, and power and performance measurement. The successful candidate will work with a small team to build and run testbenches, analyze cove

Easy Apply

Full-time

$70 - $80 per hour

Senior Emulation Engineer

San Jose, California

•

Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 138,000.00 - 206,000.00 per year

Senior SoC Verification/Validation Engineer

San Jose, California

•

Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 165,000.00 per year

Principal Emulation Engineer

San Jose, California

•

Today

Full-time

USD 209,000.00 per year

Zebu jobs in California, USA