In-Person Interview Required Design Verification Engineer Minneapolis, MN 9 + Months Role: Full DV ownership of a custom 36 I/O die-to-die PHY test chip from planning to tape-out. What You'll Do: Build UVM/SystemVerilog testbenches from scratch. Verify custom blocks: Eye Monitor, PRBS Error Counter, and I2C Interface. Implement SVA and Formal Verification (JasperGold/VC Formal). Manage regressions and provide post-silicon bring-up support. What You Bring: BS/MS/PhD in EE, CE, or related fie