We are seeking a Senior / Principal ASIC Designer to lead micro-architecture and RTL implementation for a high-performance scale-up switch ASIC. This role focuses on translating architecture into high-quality RTL optimized for advanced nodes. Key Responsibilities - Define micro-architecture for key blocks - Develop RTL using SystemVerilog and Verilog - Optimize for power, performance, and area - Implement high-speed datapaths and pipelines - Work with physical design for timing closure - Supp