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San Jose, California

•

Today

We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute SoC-level validation and performance verification strategyBuild system-level testbenches, workloads, and performance modelsAnalyze performance bottlenecks acros

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Full-time

160000 - 175000

Senior Design Verification Engineer

San Jose, California

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7d ago

Immediate need for a talented Senior Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Jose, CA(Onsite). Please review the job description below and contact me ASAP if you are interested. Job ID:26-19462 Pay Range: $150000 - $160000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Key Responsibilities: Design and develo

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Full-time

$150,000 - $160,000

Design Verification Engineer - Ethernet

Santa Clara, California

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26d ago

Design Verification Engineer Overview Upscale AI is developing next-generation Ethernet networking infrastructure optimized for large-scale AI and GPU cluster environments. We are seeking experienced Design Verification Engineers with strong networking and ASIC verification backgrounds to help validate high-performance networking silicon and AI fabric technologies. ResponsibilitiesDevelop and execute verification plans for networking ASICs and SoC designsBuild and maintain SystemVerilog/UVM-base

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Full-time

USD180000 - USD300000 per annum, Benefits: $180k-$300k Annual Salary

Senior Design Verification Engineer-Need local To CA

Sunnyvale, California

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18d ago

Role: Senior Design Verification Engineer Location -Sunnyvale, CA-Onsite No of Positions - 2 Exp needed - 8 to 10 yrs Duration - Longterm Here is the JD: Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause, and res

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Third Party, Contract

$70 - $80

Design Verification Engineer (ASIC/SoC verification) - Remote

Remote or Arkansas

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Today

Role: Design Verification Engineer Remote (must be aligned with PST time zone) Job Type: Contract Job Description: We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. Qualifications: B.S. or M.S. in Elec

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Full-time, Contract, Third Party

ASIC / SoC RTL Design Engineer

San Jose, California

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Today

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS SoC design using ARM, PCIe, DDR, and Ethernet. Responsibilities: Architecture definition and micro-specs RTL coding, verification, and debug Synthesis, timing closure, and bring-up Requirements: ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,

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Contract

$60 - $62.50 per hour

RTL Design Engineer / Design Verification Engineer

Remote

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5d ago

R-069895 RTL Design Engineer Wireless SoC (Remote PST) Location: Remote (must be aligned with PST time zone / willing to work PST hours) We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Required Skills 5+ years of hands-on RTL design experience (

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Full-time, Third Party

Depends on Experience

Design Verification Engineer

Remote

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6d ago

Role Design Verification Engineer Location - Remote (must be aligned with PST time zone) Job Description and other details We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with

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Contract, Third Party

Depends on Experience

Staff/Principal Engineer - Design Verification (SoC expert/lead)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: ASIC Design Verification SoC Lead (Technical lead role) Position Description: This is a position for lead member in Micron's ASIC Verification and Emulation group.

Full-time

USD 168,000.00 - 336,000.00 per year

SoC Verification Engineer - NoC / UVM

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

Senior SoC Verification/Validation Engineer

San Jose, California

•

Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 165,000.00 per year

Staff Engineer, Design Verification

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 113,920.00 - 170,600.00 per year

Senior Staff Engineer, Design Verification

Santa Clara, California

•

Today

Full-time

USD 134,390.00 - 201,300.00 per year

Staff/Principal Engineer. ASIC Design Verification (DDR expert)

San Jose, California

•

Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff/Principal ASIC SoC Design Verification Engineer - DDR expert (Technical role) Position Description: This is a position for Staff technical member of Micron's

Full-time

USD 168,000.00 - 336,000.00 per year

ASIC RTL Design Engineer - Onsite

San Jose, California

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28d ago

Title: ASIC RTL Design Engineer - Onsite Mandatory skills: SoC Architecture, ASIC design flow, RTL coding, debugging, verification, supporting synthesis, timing closure, ARM cores, I/O standard interfaces, Ethernet, DDR, DMA, PCIE, SATA, internal IPs, digital CMOS processes, SoC design, Chip definition, Architecture development, modeling, micro-architectural specifications, micro-architectural specifications, logic implementation, emulation, debug Description: JOB DUTIES: The work will expose th

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Contract

57 - 62

Principal Engineer, Design Verification - DDR Memory Subsystems

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, edge computing, and embedded systems. About the Role

Full-time

USD 209,500.00 - 299,200.00 per year

Staff Engineer, ASIC Design Verification

San Jose, California

•

Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 163,000.00 - 253,000.00 per year

ASIC Physical Design Engineer

San Jose, California

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7d ago

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Great base pay, bonus, terrific benefits and exceptional 401k! he MissionStaffRight Associates is recruiting to identify a high-caliber ASICPhysical Design Engineer to spearhead the structural realization of next-generation System-on-Chip (So

Easy Apply

Full-time

170000 - 220000

SoC Power Validation Engineer

Cupertino, California

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Today

As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you will help design products that bring to our customers experiences they've never before envisioned! You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASI

Full-time

ATE Test Engineer

Mountain View, California

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29d ago

Title: ATE Test Engineer Location: Mountain View, CA- Onsite work Client/ Customer- Salary: Market FTE/ Fulltime preferred JC: 141462 Key Responsibilities: Develop and debug ATE test programs for IP and SoC devices. Perform IP-level characterization and validation. Execute functional tests including HSIO, DDR, and vector-based testing. Work on SMT8/93K or similar ATE platforms. Support translation of functional models into production test vectors. Collaborate with design, DV, and product e

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Full-time

Depends on Experience

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