Position: Static Timing Analysis Engineer Location - San Jose, CA, USA What You will Do: Develop and validate timing constraints for intricate SoC designs. Expertise in Synthesis, Equivalency Checking and STA Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus. Experience with Synopsys Tools Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA Define and implement timing signoff method