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Static Timing Analysis Engineer

Apetan Consulting

San Jose, California • Today

Easy Apply

Full-time

Depends on Experience

Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

Altera Corp.

San Jose, California • Today

Full-time

USD 187,000.00 - 270,000.00 per year

STA Lead Static Timing Analysis

Metalight Solutions Inc

Remote • 14d ago

Easy Apply

Contract

Depends on Experience

Principal Application Engineer- Timing Sign Off

Synopsys, Inc.

Sunnyvale, California • 22d ago

Full-time

STA Engineer

Qualcomm

Santa Clara, California • Today

Full-time

Compensation information provided in the description

CPU STA CAD Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 209,300.00 - 313,900.00 per year

ASIC Implementation Engineer STA

Broadcom Corporation

San Jose, California • Today

Full-time

USD 143,800.00 - 230,000.00 per year

Sr. Failure Analysis Engineer

SiTime

Santa Clara, California • Today

Full-time

USD 124,930.00 - 171,770.00 per year

Sr. Timing Methodology Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 124,040.00 per year

STA Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 159,600.00 - 239,400.00 per year

Senior FEA Engineer

Apple, Inc.

Cupertino, California • Today

Full-time

REQ: STA Engineer in San Jose, CA.

Aita Consulting Services,Inc.

San Jose, California • Today

Easy Apply

Full-time, Third Party

$180000 - $250000

Senior Mechanical Engineer - FEA Analysis & Test

Kodiak

Mountain View, California • Today

Full-time

USD 150,000.00 - 185,000.00 per year

Senior Static Timing Analysis (STA) Methodology Engineer

E-Space

Santa Clara, California • Today

Full-time

USD 120,000.00 - 220,000.00 per year

CPU Physical Electrical Analysis Engineer

Apple, Inc.

Santa Clara, California • Today

Full-time

CPU CDC/STA Engineer

Apple, Inc.

Santa Clara, California • Today

Full-time

Senior Staff Physical Verification CAD engineer

Marvell Semiconductor Inc.

Santa Clara, California • Today

Full-time

USD 127,630.00 - 191,200.00 per year

Job Details

Skills

synthesis tools
SoC
Static Timing Analysis
quality of results

Summary

Position: Static Timing Analysis Engineer

Locations: San Jose, San Diego, Irvine, CA (Onsite)

What You Will Do:

Develop and validate timing constraints for intricate SoC designs.
Expertise in Synthesis, Equivalency Checking and STA.
Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus.
Experience with Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA.
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
Conduct pre-route timing checks and quality of results (QoR) analysis.
Automate timing analysis processes using scripting languages such as Tcl or Perl.
Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
Ensure compliance with timing signoff checklists and criteria.

What You Will Bring:

Experience with high-complexity silicon in advanced technology nodes.
Familiarity with timing constraint development for hierarchical designs.
Knowledge of clock tree planning and implementation for SoCs.
Experience with timing ECO creation and final timing signoff.
Proficiency in using STA tools such as PrimeTime, TCM, Tempus and scripting languages such as Tcl, Perl.
Proficiency in using synthesis tools (Genus).
Must have Full Chip (Top Level), Block Level and Multi-voltage Timing Closure experience.
Debug and Fix Timing Issues.
This STA engineer needs to do Synthesis, Equivalency Checking and STA.
Good understanding of Timing Constraints, Exceptions, CTS and clock constraints, Multi-Mode Multi-Corner timing closure expertise.
Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA.
Strong understanding of ASIC design flows, including RTL and place-and-route.
Excellent problem-solving skills and attention to detail.
Effective communication and teamwork abilities.

Education and Experience:

Bachelor’s and 8+ years of related experience; at this level post-graduate coursework may be desirable.
Master’s degree and 6+ years of related experience.
PhD and 3+ years of related experience.

Work Requirements:

This role is considered an on-site position located in San Jose.
You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10513292
Position Id: 73983-12895-1791477308
Posted 13 hours ago

Fitment

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Similar Jobs

STA Engineer

Santa Clara, California

•

Today

Company:Qualcomm Atheros, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-systems.

Full-time

Compensation information provided in the description

REQ: STA Engineer in San Jose, CA.

San Jose, California

•

Today

Hi, One of our clients is looking forSTA Engineer in San Jose, CA. Title:STA Engineer Location:San Jose, CA. Duration:Full Time Job Description: Responsibilities Include: Develop and validate timing constraints for intricate SoC designs. Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus). Define and implement timing signoff methodologies, including process corners, derates, and uncertainties. Conduct pre-route timing checks an

Easy Apply

Full-time, Third Party

$180000 - $250000

Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

San Jose, California

•

Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 187,000.00 - 270,000.00 per year

Physical Design Engineer – Lead

San Jose, California

•

Today

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

Easy Apply

Full-time

Depends on Experience

Job Details

Skills

synthesis tools
SoC
Static Timing Analysis
quality of results

Summary

Position: Static Timing Analysis Engineer

Locations: San Jose, San Diego, Irvine, CA (Onsite)

What You Will Do:

Develop and validate timing constraints for intricate SoC designs.
Expertise in Synthesis, Equivalency Checking and STA.
Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus.
Experience with Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA.
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
Conduct pre-route timing checks and quality of results (QoR) analysis.
Automate timing analysis processes using scripting languages such as Tcl or Perl.
Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
Ensure compliance with timing signoff checklists and criteria.

What You Will Bring:

Experience with high-complexity silicon in advanced technology nodes.
Familiarity with timing constraint development for hierarchical designs.
Knowledge of clock tree planning and implementation for SoCs.
Experience with timing ECO creation and final timing signoff.
Proficiency in using STA tools such as PrimeTime, TCM, Tempus and scripting languages such as Tcl, Perl.
Proficiency in using synthesis tools (Genus).
Must have Full Chip (Top Level), Block Level and Multi-voltage Timing Closure experience.
Debug and Fix Timing Issues.
This STA engineer needs to do Synthesis, Equivalency Checking and STA.
Good understanding of Timing Constraints, Exceptions, CTS and clock constraints, Multi-Mode Multi-Corner timing closure expertise.
Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA.
Strong understanding of ASIC design flows, including RTL and place-and-route.
Excellent problem-solving skills and attention to detail.
Effective communication and teamwork abilities.

Education and Experience:

Bachelor’s and 8+ years of related experience; at this level post-graduate coursework may be desirable.
Master’s degree and 6+ years of related experience.
PhD and 3+ years of related experience.

Work Requirements:

This role is considered an on-site position located in San Jose.
You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.

Dice Id: 10513292
Position Id: 73983-12895-1791477308
Posted 13 hours ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

STA Engineer

Santa Clara, California

•

Today

Full-time

Compensation information provided in the description

REQ: STA Engineer in San Jose, CA.

San Jose, California

•

Today

Easy Apply

Full-time, Third Party

$180000 - $250000

Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

San Jose, California

•

Today

Full-time

USD 187,000.00 - 270,000.00 per year

Physical Design Engineer – Lead

San Jose, California

•

Today

Easy Apply

Full-time

Depends on Experience