RTL/ASIC Design Engineer San Jose, CA (100% Onsite) 12 + Months $75-78/HR Must-Haves: 5-6+ years ASIC/RTL design experience Proven tape-outs on production silicon SOC RTL block design & IP integration Lint, CDC, RDC experience Synthesis & static timing analysis Responsibilities: Write micro-architecture docs; own block design & implementation (timing, area, power) Partner with arch, verification, and physical design teams through tape-out Support silicon bring-up and cross-functional problem s