ASIC Physical Design Engineer

We are looking for a Senior ASIC/RTL Design Engineer for our client in San Jose, CA Job Title: Senior ASIC/RTL Design Engineer Job Location: San Jose, CA Job Type: Contract Job Description: Pay Range: $62.45hr - $78.78hrRequirement/Must Have: 5+ years of ASIC design experience.Proven track record of ASIC design across multiple production tape-outs.Experience designing RTL blocks for SoC architectures.Experience integrating ASIC IP into SoCs.Experience with linting, CDC, and RDC methodologies.Ex

Looking for an Innovative Staff Full-Chip Timing (STA) Engineer - On Site This Jobot Job is hosted by: Lindsey Cusic Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $175,000 - $235,000 per year A bit about us: We are a growing semiconductor design organization focused on advanced ASIC and SoC development. Our team is built around deep technical expertise, fast execution, and a strong ownership mindset. We work on complex, high-performance

Job Title: DFT Engineer (6+ Years) Location: Santa Clara, California, USA Employment Type: Full-Time Job Summary We are seeking a highly skilled and motivated DFT Engineer with 6+ years of experience to join our team in Santa Clara, CA. The ideal candidate will have strong expertise in Design for Testability (DFT) methodologies, test insertion, and validation for complex SoCs. You will work closely with design, verification, and product engineering teams to ensure high-quality, testable silicon

Title: Systems Design Engineer - Emulation and Prototyping - Hybrid Mandatory skills: hardware design, FPGA Design, Synopsys HAPS, Zebu, Protium, Palladium, FPGA, emulation platforms, RTL Design, Verilog, System Verilog, Emulation Platform, Prototyping Platform, SoC designs, RTL coding, AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes links, debugging tools, RTL, Verdi, fsdb analysis, ASIC design flows, emulation, scripting, automation, Python, Perl, Tcl, Make, CMake, Shell, RTL patches, model creatio