The ideal candidate should have strong relevant and recent technical and hands-on background
and be able is hit the ground running as an individual contributor
• Contribute to, or lead, PCB and package substrate layout development for leading-edge
Optical communication products
• Ensure compliance with IPC standards, company design practices, and fabrication
capabilities.
• Collaborate with electrical, mechanical, thermal, signal-integrity, power-integrity, and
manufacturing teams.
• Work with PCB fabricators, and substrate vendors to close DFMs.
Minimum Requirements
• Bachelor’s degree or equivalent certifications with a minimum of 10+ years of relevant
industry experience in PCB board and/or package substrate layout engineering.
• Expert-level proficiency with Cadence Allegro PCB design tools
• Strong demonstrated working experience of complex high-density, high-speed PCB and
substrate designs using advanced HDI, stacked micro-via, sequential lamination, and fine-pitch
BGA technologies.
• Hands-on experience with complex multilayer high-density organic substrates, fine-pitch
BGAs, and advanced component packages.
• Working understanding of transmission line layout geometries and rules (micro strip,
strip line, CPW, etc.)
• Demonstrated experience in layout of compact low voltage and high current multiphase
DC-DC power converters for state-of-the-art processors and GPUs
• Strong understanding of PCB fabrication, assembly processes, DFM, and manufacturing
tolerances.
• Demonstrated success delivering high-volume, high-reliability communication products
under aggressive schedules.
Highly Desired Skills
• Demonstrated experience with mSAP PCB layout design
• Demonstrated experience with layout design of state of art optical pluggable products
(CFP2, QSFP-DD, OSFP)
• Proficiency in Cadence SiP tools and Substrate layout techniques
• Proficiency in layout of designs with Wire Bond components
• Strong understanding of PCB fabrication and assembly processes
• Strong knowledge of relevant industry standards (IPC Class 2/3, JEDEC, etc.)
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