DFT Engineers - Multiple roles

Job Title: DFT EngineerLocation: Santa Clara, CA (Onsite)Job Type: Fulltime Job SummaryWe are seeking an experienced DFT Engineer with strong expertise in Design for Testability (DFT) and Automatic Test Pattern Generation (ATPG) for SoC and ASIC designs. The ideal candidate will be responsible for implementing and validating DFT architectures, generating ATPG patterns, supporting MBIST implementation, and ensuring high test coverage for complex semiconductor products. Key Responsibilities< data-

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin

Job Title : Senior DFT Engineer Location : Santa Clara, CA Experience : 4+ Years in DFT Skill: [ATPG , MBIST, IO Test, Clock Verification] Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The enginee

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