Physical Design Engineer

Location: Palo Alto, CA (Full Onsite) Exposure to TSMC 2NP/3NP is must Perform endtoend physical design flow: oFloorplanning oPower planning (PG grid, IR) oPlacement & optimization oCTS (Clock Tree Synthesis) oRouting oPostroute optimization Achieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations Handle lowpower design techniques: oMultiVt, Multivoltage (UPF) oPower gating, clock gating Perform physical verification and signoff: oSTA (Primetime) oSI / Cro

Job Title: Physical Design Engineer Location: Palo Alto, CA // Onsite Only local candidates allowed Duration: 6-12+ Months Contract Job Description: Exposure to TSMC 2NP/3NP is must Perform endtoend physical design flow: FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations Handle lowpower design techniques: MultiVt, Multivoltage (UPF

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

Job Title: Physical Design Engineer Location: San Jose CA Contract We are seeking a Physical Design contractor with strong synthesis and implementationexpertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designsDrive PPA (power, performance, area) optimization through synthesis and earlyimplementation stages. Develop and refine floorplans using Cadence InnovusCollaborate c