1 - 20 of 228 Jobs

Senior ASIC / FPGA Design Engineer

CIENA Corporation

On-site in Gilbert, Arizona, USA

Full-time

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual's passions, growth, wellbeing and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact. Not ready to apply? Join ourTalent Communityto get relevant job alerts straight to your inbox. Why Ciena: You will be a member of

Senior ASIC / FPGA Design Engineer

CIENA Corporation

On-site in Petaluma, California, USA

Full-time

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual's passions, growth, wellbeing and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact. Not ready to apply? Join ourTalent Communityto get relevant job alerts straight to your inbox. Why Ciena: You will be a member of

RTL/ASIC Design Engineer

Netwoven

Hybrid in San Jose, California, USA

Contract

KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project s schedule. Help to improve/automate design process. Support post-silicon product bring-up/debug. PREFERRED EXPERIENCE: 10 years' experience in RTL coding Knowledge of PCIe Gen5 and PIPE specification Kno

ASIC Physical Designers - I

Infobahn Softworld Inc.

US

Contract

Description: LAPTOP WILL BE PROVIDED Education requirement: Minimum high school diploma / GED *MRUNDA is required* Same sponsor for JP25789 and JP25794; duplicates are not accepted Hybrid Work Model - mostly working from home with 1-2days in the office. DO NOT SUBMIT REMOTE ONLY CANDIDATES CW will assist the DE Leads in executing physical design including Performance Verification involving layout verification and reliability checks. Required Skills: Physical design CAD flows and Design verifi

ASIC & FPGA Design Engineer

Technical Link

Hybrid in Dallas, Texas, USA

Contract

ASIC & FPGA Design Engineering Candidate must have ability to Obtain Secret Clearance. Clearance not needed to start. Job Description: Seeking a Digital Design FPGA Engineer with Cost Account Management and supplier manage experience. Major tasks include supplier management and oversight as well as system integration and test support. Additional activities include design evaluation, coordination of test activities among across various functions, provide inputs to formal documentation, and suppor

Technical Business Development Manager with ASIC, Foundry and designing knowledge

Epikso

On-site in San Jose, California, USA

Full-time

Sr. BDM role San Jose CA. Hybrid role Direct Hire permanent opportunity Salary Range: $170K-$240K as base salary + bonus + benefits Developing company.link's business to provide access to advanced ASIC foundry technologies to Small and Medium Businesses (SMBs) and to larger companies in North America. What you will do The IC-link division of the company is responsible for providing access to advanced ASIC foundry technologies to Small and Medium Businesses (SMBs) and to larger companies for

ASIC Physical Designers @ Austin, TX - Hybrid

Infobahn Softworld Inc.

On-site in Austin, Texas, USA

Contract

Job Title: ASIC Physical Designers Location: Austin, TX Hybrid - (Required to work onsite every Wednesday) Duration: 6+ months Laptop will be issued Description: The hire will be involved in deep sub-micron IC logic and VLSI, ASIC and Custom Design, with Intel's PROM IP for use in mobile, IOT, client, network, and server segments. We are looking for a skilled and motivated VLSI Circuit Design Engineer to join our dynamic team and contribute to our mission of shaping the future of semiconduct

Senior ASIC Engineer

Della Infotech

On-site in San Diego, California, USA

Contract

Position: Senior ASIC Engineer Location: San Diego, CA (Candidate needs to work Day 1 onsite) Work Arrangement Fully On-Site Duration: 12 Months Experience level: 8- 15 Years This role has strong experience in System Verilog, UVM, DDR PHY / LPDDR protocol, Power-aware simulations. What You'll Be Doing: Work involves executing complete verification project in the role of Senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and clos

ASIC/LPDRAM Design Engineer

Object Technology Solutions, Inc.

Remote

Contract

Description: Understand the LPDRAM state machine and develop the hardware models for DRAM features and the related validation test bench. Develop memory controller models, including request scheduling, address mapping etc., to enable new DRAM features. Develop the automation test scripts using Python to improve the overall simulation methodologies. Develop new DRAM technology changes per the spec and the state machine and the validation test bench. Experience in System C, LPDRAM, IP Simulat

Senior ASIC / FPGA Design Verification Engineer with UVM

Technical Link

On-site in Los Angeles, California, USA

Contract

Title: ASIC/FPGA Design Verification Engineer - Onsite in Los Angles, CA (6-12 Month Contract) Job Description: Develop UVM simulation plan based on design specs. Customize or create UVC, Scoreboard, Monitor, and test cases. Ensure functional and code coverage meets project thresholds. Document results. Expectations for Contractors: Ideally, capable of handling complex blocks independently.Responsible for interface or functional block verification.Develop test plans adhering to provided templat

RTL ASIC Design Engineer

Innova Solutions, Inc

On-site in San Jose, California, USA

Full-time

Innova Solutions is immediately hiring for an RTL ASIC Design Engineer. Job Title: RTL ASIC Design Engineer Location: San Jose, CA, USA Contract Duration: Full Time As an RTL ASIC Design Engineer, you will: Generate and retarget IP level tests to full chip.You would have to simulate IP tests,Debugging simulation failures to root cause them,Fixing test issues.You would have to verify design fixes. Qualified candidates should APPLY NOW for immediate consideration! Please hit APPLY to provide the

ASIC Power Engineer

Apple, Inc.

On-site in San Diego, California, USA

Full-time

Summary Do you like to work on ground breaking technologies that enable amazing new products? Do you have the attention for details and love for excellence to work towards an extraordinary result? Envision what you could do here! At Apple, we believe new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Key Qualifications Hands on experience with PTPX

ASIC Power Engineer

Apple, Inc.

On-site in Sunnyvale, California, USA

Full-time

Summary Do you like to work on ground breaking technologies that enable amazing new products? Do you have the attention for details and love for excellence to work towards an extraordinary result? Envision what you could do here! At Apple, we believe new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Key Qualifications Hands on experience with PTPX

ASIC Design Engineer

Apple, Inc.

On-site in Cupertino, California, USA

Full-time

Summary As an ASIC Design Engineer, the individual's primary responsibility will be RTL design. This will include chip architecture definition, block/function definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs. Key Qualifications Proven track-record in digital design including RTL design experienceStrong understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back

Touch ASIC Architect (Analog)

Apple, Inc.

On-site in Cupertino, California, USA

Full-time

Summary Design, develop, and launch next-generation Touch Technologies in Apple products!The Touch Technology team develops ground breaking Touch solutions and technologies that are central to Apple's products, including the iPhone, iPad, MacBooks, and more! The key goal of our team is to enable the world's best multi-touch user-experience. Our team features a collaborative and hands-on environment that fosters engineering excellence, creativity, and innovation. An ASIC Analog Architect within

Touch ASIC Architect (Analog)

Apple, Inc.

On-site in San Diego, California, USA

Full-time

Summary Design, develop, and launch next-generation Touch Technologies in Apple products!The Touch Technology team develops ground breaking Touch solutions and technologies that are central to Apple's products, including the iPhone, iPad, MacBooks, and more! The key goal of our team is to enable the world's best multi-touch user-experience. Our team features a collaborative and hands-on environment that fosters engineering excellence, creativity, and innovation. An ASIC Analog Architect within

Touch ASIC Architect (Analog)

Apple, Inc.

On-site in Cupertino, California, USA

Full-time

Summary Design, develop, and launch next-generation Touch Technologies in Apple products!The Touch Technology team develops ground breaking Touch solutions and technologies that are central to Apple's products, including the iPhone, iPad, MacBooks, and more! The key goal of our team is to enable the world's best multi-touch user-experience. Our team features a collaborative and hands-on environment that fosters engineering excellence, creativity, and innovation. An ASIC Analog Architect within

ASIC Power Engineer

Apple, Inc.

On-site in Cupertino, California, USA

Full-time

Summary Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC/Power architecture and design, VLS

Touch ASIC Architect (Digital)

Apple, Inc.

On-site in Cupertino, California, USA

Full-time

Summary Design, develop, and launch next-generation Touch Technologies in Apple products!The Touch Technology team develops ground breaking Touch solutions and technologies that are central to Apple's products, including the iPhone, iPad, MacBooks, and more! The key goal of our team is to enable the world's best multi-touch user-experience. Our team features a collaborative and hands-on environment that fosters engineering excellence, creativity, and innovation. An ASIC Digital Architect within

Touch ASIC Architect (Digital)

Apple, Inc.

On-site in San Diego, California, USA

Full-time

Summary Design, develop, and launch next-generation Touch Technologies in Apple products!The Touch Technology team develops ground breaking Touch solutions and technologies that are central to Apple's products, including the iPhone, iPad, MacBooks, and more! The key goal of our team is to enable the world's best multi-touch user-experience. Our team features a collaborative and hands-on environment that fosters engineering excellence, creativity, and innovation. An ASIC Digital Architect within