ASIC Jobs

1 - 20 of 15,946 Jobs

Senior Front-End ASIC EngineerJob Title - Senior Front-End ASIC Engineer

DivTek Global Solutions Inc.Company Name - DivTek Global Solutions Inc.

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San Jose, California, USA

Full-time

Job Title: Senior Front-End ASIC Engineer Job Location: San Jose, CA (Hybrid) Benefits: Excellent PTO, full benefits, 401(k), hybrid schedule, great team culture Job Type: Full-Time, Permanent About Company: This is a full-time role, directly employed position through the client. Work Schedule Type: This is a hybrid position Relocation: Relocation assistance available Job Description Our client is seeking a Senior Front-End ASIC Engineer to join their elite engineering team. This is a unique op

Sr. Package Design Engineer ASIC/SOCJob Title - Sr. Package Design Engineer ASIC/SOC

DivTek Global Solutions Inc.Company Name - DivTek Global Solutions Inc.

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San Jose, California, USA

Full-time

Job Title Sr. Package Design Engineer ASIC/SOC Job Location: San Jose, CA (Hybrid) Benefits: Excellent PTO, full benefits, 401(k), hybrid schedule, great team culture Job Type: Full-Time, Permanent About Company: This is a full-time role, directly employed position through the client. Work Schedule Type: This is a hybrid position Relocation: Relocation assistance available The Role: Sr. Package Design Engineer We are seeking a highly experienced Package Design Engineer with 7+ years of hands-on

Technical Program Manager (TPM) ASIC / SoCJob Title - Technical Program Manager (TPM) ASIC / SoC

DivTek Global Solutions Inc.Company Name - DivTek Global Solutions Inc.

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San Jose, California, USA

Full-time

Job Title: Technical Program Manager (TPM) ASIC / SoC Hybrid San Jose, CA Job Location: San Jose, CA (Hybrid) Benefits: Excellent PTO, full benefits, 401(k), hybrid schedule, great team culture Job Type: Full-Time, Permanent About Company: This is a full-time role, directly employed position through the client. Work Schedule Type: This is a hybrid position Relocation: Relocation assistance available Position Overview Technical Program Manager (TPM): We are seeking a hands-on Technical Program

Physical Design Engineer Custom ASIC / SoCJob Title - Physical Design Engineer Custom ASIC / SoC

DivTek Global Solutions Inc.Company Name - DivTek Global Solutions Inc.

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San Jose, California, USA

Full-time

Job Title: Physical Design Engineer Custom ASIC / SoC Hybrid San Jose, CA Job Location: San Jose, CA (Hybrid) Benefits: Excellent PTO, full benefits, 401(k), hybrid schedule, great team culture Job Type: Full-Time, Permanent About Company: This is a full-time role, directly employed position through the client. Work Schedule Type: This is a hybrid position Relocation: Relocation assistance available Position Overview Physical Design Engineer: We are seeking a hands-on Physical Design Engineer w

ASIC/SOC Emulation EngineerJob Title - ASIC/SOC Emulation Engineer

INFT Solutions incCompany Name - INFT Solutions inc

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Full-time, Part-time, Contract, Third Party

Role: ASIC/SOC Emulation Engineer Work location: Santa Clara, CA. Job Description: "ASIC Emulation Engineer Develop emulation testbenches in System Verilog and/or C/C++. Deliver emulation and prototyping models from RTL on industry standard emulation and prototyping platforms. Build and execute emulation test plan to ensure quality of the models and assist pre-silicon validation. Drive emulation methodologies for HW verification and SW development. Develop emulation tools, workflows, and infras

FPGA/ASIC Verification Engineer (Silicon Engineering)Job Title - FPGA/ASIC Verification Engineer (Silicon Engineering)

SpaceXCompany Name - SpaceX

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Sunnyvale, California, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. FPGA/ASIC VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is th

ASIC Engineer, Design VerificationJob Title - ASIC Engineer, Design Verification

Meta Platforms, Inc. (f/k/a Facebook, Inc.)Company Name - Meta Platforms, Inc. (f/k/a Facebook, Inc.)

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Remote

Full-time

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Menlo Park, CA ASIC Engineer, Design Verification: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification and develop functional tests based on verification test plan. Telecommute from anywhere in the U.S. permitted. (ref. code REQ-2506-152460: $238,228/year - $287,650/year). Individual pay is determined by skills, qualifications, experience, and loca

Sr Director, ASIC EngineeringJob Title - Sr Director, ASIC Engineering

PaloAlto NetworksCompany Name - PaloAlto Networks

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Santa Clara, California, USA

Full-time

Company Description Our Mission At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we're looking for innovators who are as committed to shaping the future of cybersecurity as we are. Who We Are We take our mission of

FPGA/ASIC Design Engineer (Silicon Engineering)Job Title - FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceXCompany Name - SpaceX

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Redmond, Washington, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the worl

FPGA/ASIC Design Engineer (Silicon Engineering)Job Title - FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceXCompany Name - SpaceX

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Irvine, California, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the worl

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration teamJob Title - Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Annapurna Labs (U.S.) Inc.Company Name - Annapurna Labs (U.S.) Inc.

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Austin, Texas, USA

Full-time

Utility Computing (UC)AWS Utility Computing (UC) provides product innovations - from foundational services such as Amazon's Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS's services and features apart in the industry. As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS,

ASIC Design Engineer STA & SDC SpecialistJob Title - ASIC Design Engineer STA & SDC Specialist

Della InfotechCompany Name - Della Infotech

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San Jose, California, USA

Third Party, Contract

Minimum Qualifications Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience Experience with block/full chip SDC development in functional and test modes. Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus Understanding of related digital design concepts (eg. clocking and async boundaries) Experience

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration teamJob Title - Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Annapurna Labs (U.S.) Inc.Company Name - Annapurna Labs (U.S.) Inc.

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Austin, Texas, USA

Full-time

Utility Computing (UC) AWS Utility Computing (UC) provides product innovations - from foundational services such as Amazon's Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS's services and features apart in the industry. As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS

Senior Design Verification EngineerJob Title - Senior Design Verification Engineer

SivaltechCompany Name - Sivaltech

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San Diego, California, USA

Contract

Job descriptionCompany Description Sivaltech is a well-established ASIC/FPGA, Analog, and Embedded Software design services company with offices in California, USA, and Bangalore, India. We are a preferred design services partner for both Fortune 500 companies and startups in the semiconductor industry. With expertise spanning GPUs, CPUs, wireless, communications, medical, broadband, and consumer electronics, Sivaltech is well-equipped to address our clients' complex design challenges. Role Desc

Senior ASIC Engineer, Static Timing AnalysisJob Title - Senior ASIC Engineer, Static Timing Analysis

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

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Santa Clara, California, USA

Third Party, Contract

Role Title: Senior ASIC Engineer, Static Timing Analysis Location: San Jose, CA Onsite Alternate location: Colorado office - Longmont Remote is an option for right fit Duration: 12+ months contract Description: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA

ASIC/FPGA Research Engineer - Digital DesignJob Title - ASIC/FPGA Research Engineer - Digital Design

University of Southern CaliforniaCompany Name - University of Southern California

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Arlington, Virginia, USA

Full-time

USC's Information Sciences Institute (ISI), a unit of the university's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI's 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA. Perform digital hardware design in a fast-movin

ASIC & FPGA Design EngineeringJob Title - ASIC & FPGA Design Engineering

Judge Group, Inc.Company Name - Judge Group, Inc.

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Orlando, Florida, USA

Full-time

Location: Orlando, FL Description: Role - Asic & Fpga Design Engineering Type: Contract Location - ( Onsite) Job Description: Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses spe

Senior ASIC Engineer, Static Timing Analysis (STA), PT/DC checks @ San Jose, CA/Longmont, COJob Title - Senior ASIC Engineer, Static Timing Analysis (STA), PT/DC checks @ San Jose, CA/Longmont, CO

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

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Richardson, Texas, USA

Contract

We have an immediate opportunity with one of our direct clients. Please find the job description below and if you are interested, please forward your resume and share below details: Best contact number: Work Authorization: Hourly Payrate expected: Month & Day of birth (MM/DD): Present Location & Zip-code: LinkedIn: Title: Senior ASIC Engineer, Static Timing Analysis (STA) Location: San Jose, CA- Onsite. Alternate location: Colorado office - 3100 Logic Dr, Longmont Duration: 12+ months R

Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASICJob Title - Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASIC

Motion Recruitment Partners, LLCCompany Name - Motion Recruitment Partners, LLC

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Irvine, California, USA

Full-time

Our client is a glbal infrastructure technology leader built on more than 60 years of innovation within the semiconndutor and Manufacturing space for communications. They are urgently seeking a Sr. level Digital Signal Processing (DSP) R&D Engineer to join their growing team. Responsibilities include: Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation Develop and

Senior Asic EngineerJob Title - Senior Asic Engineer

Aditi ConsultingCompany Name - Aditi Consulting

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California, USA

Full-time

Salary: $280k - $300k/Yr. Responsibilities: Define and architect packet processing pipelines including related lookup tables and metadata structures for high-performance networking ASICs, including ingress/egress processing, switching/bridging and routing, hash tables and memory lookups, classification, ACL, various tunneling protocols like VxLAN, GRE, IPinIP, QoS, scheduling, traffic management, and congestion control. Work closely with the CTO to translate high-level system requirements and c