DFT jobs in San Leandro, CA

Principal DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 220,000.00 - 355,000.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Design for Test (DFT) Engineer

Hybrid in Santa Clara, California

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13d ago

Title: Design for Test (DFT) Engineer Location: Hybrid (Travel to Santa Clara) Duration: 1year Key Skills & Experience 3+ years of experience working as a DFT Engineer.Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improv

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Contract

Depends on Experience

DFT Engineer

Mountain View, California

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4d ago

Hi, Job Title : DFT Engineer (Scan / MBIST / ATPG) Location: Mountain View CA DFT Engineer (Scan / MBIST / ATPG) We are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs. Thanks and Regards, Praveenkumar

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Full-time, Third Party

Depends on Experience

Senior DFT Engineer

Santa Clara, California

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Today

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multic

Full-time

USD 196,000.00 - 310,500.00 per year

DFT (Design for Testability)

Santa Clara, California

•

Today

Hi, Hope you are doing good, My name is Gangadhar Reddy, and I'm a Delivery Lead at Intellectt Inc. I came across your profile and believe your experience could be a good match for an exciting opportunity I'm currently working on. We are hiring a DFT Engineer for a Full-Time opportunity in Santa Clara, CA.

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Full-time

DFT Engineers

Santa Clara, California

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3d ago

Position Title: DFT Engineers Location: Santa Clara, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and MBIST MBIST Repair Implementation and Verification Generating collaterals for Test Timing and Place and Route Expertise in IJTAG 1687 standard and good at understanding ICL and PDL standard Spec Verification of DFT features including Boundary Scan JTAG SCAN MBIST High Speed IO

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Full-time, Third Party

Depends on Experience

DFT Engineer

Santa Clara, California

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5d ago

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Required Skills & Qualifications 4+ years of hands-on experience in DFT and ATPGfor SoC or ASIC designsStrong understanding of DFT fundamentalsincluding controllability, observability, and scan-based testingProven expertise in ATPG pattern generation, analysis, and debugExperience with MBIST, including memory test architectures and diagnosticsKnowledge of IO Tes

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Contract

Depends on Experience

DFT Engineer

Santa Clara, California

•

Today

Benefits: Day-1 Onsite Competitive salary Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite) Employment Type: Long-Term Contract Interview Process: Virtual Interviews Compensation: Based on Experience (DOE) Engagement: ANY Preference: Local candidates or those able to work onsite We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team. In this role, you will be responsible for designing and implementing De

Full-time

Compensation information provided in the description

CPU DFT Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to

Full-time

USD 142,200.00 - 213,400.00 per year

ASIC DFT Staff Engineer

Remote

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2d ago

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

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Third Party, Contract

Lead ASIC DFT Engineer

Remote

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20d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

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Third Party, Contract

110 - 120

Lead ASIC DFT Engineer

Remote

•

Today

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals

Full-time

Senior DFT Engineer

Remote

•

Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep

Full-time

USD 170,000.00 - 250,000.00 per year

DFT (Design For Test) Lead

Remote

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6d ago

Job Title: DFT (Design For Test) Lead Looking for how many contractors to fill this role?: 2 Duration: 7/27/2026 to 9/30/2027 (possibly extending longer based on project timelines) Location? US Remote Requirement: Candidate should be available to work California times, 9-5 PST**) Rounds of interview? 1st interview is phone screen, 2nd interview is with 2-3 engineers on team ASIC DFT experienced consulting engineers, lead-calibre. This project revision will at least go until September 2027

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Third Party, Contract

Depends on Experience

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 175,000.00 - 280,000.00 per year

Senior Electrical Engineer

Hybrid in Palo Alto, California

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2d ago

Senior Electric Engineer Youll own the electrical engineering team for a breakthrough stealth-stage neurotechnology and brain-computer interface (BCI) startup building an AI-powered neural interface platform. In this role, you will own the wearable electrical architecture from schematic through production, helping bring a highly integrated next-generation device to market. The platform combines cameras, spatial audio microphones, EEG sensors, Wi-Fi/BLE connectivity, and advanced power managemen

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Full-time

225000 - 250000

Physical Design Engineer & DV Engineers

Sunnyvale, California

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20d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Technical Program Manager - Hardware Engineering

Hybrid in Foster City, California

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9d ago

Client: Autonomous Vehicle/Tech Title: Technical Program Manager Hardware Development Programs Job Location: Foster City, CA Duration: ~6 Months Pay Rate: $89.60/HR (W2 ONLY) The Pay rate is commensurate with experience and is an estimated range provided by WorkGenius. Technical Program Manager Hardware Development Programs Foster City, CA (hybrid) Our Client''s Advanced Hardware Engineering team is in charge of delivering all the autonomous hardware, infotainment electronic control units a

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Contract

Staff Electrical Engineer - High Voltage Systems

San Leandro, California

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Today

About SirenOpt SirenOpt helps manufacturers make better, safer, and more reliable micro- and nano-materials. These materials are the building blocks of critical sectors of the global economy such as batteries, computer chips, aircraft components, and power systems. But, surging material demand and growing complexity are pushing production to unprecedented scales and speeds, leaving manufacturers effectively flying blind. Small, undetected variations during production lead to wastage, lower perf

Full-time

USD 160,000.00 - 240,000.00 per year

DFT jobs in San Leandro, CA, USA