Design Verification Engineer Jobs

1 - 20 of 1,176 Jobs

Design Verification EngineerJob Title - Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

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San Jose, California, USA

Contract

Job Title - Design Verification Engineer (GPU) Duration 6+ Months Location: San Jose, CA Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date I UVM version will place you among the elite within our prof

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Principal Design Verification EngineerJob Title - Principal Design Verification Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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San Jose, California, USA

Full-time

Principal Design Verification Engineer A leading chip and silicon IP provider focused on accelerating and securing data is looking to hire an outstanding Principal Design Verification Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This role offers the chance to work alongside top engineering talent on innovative products that push the boundaries of speed and data security. As a Principal Design Verification Engineer, you ll play a critical role in the development of MIC

Senior Design Verification EngineerJob Title - Senior Design Verification Engineer

PeopleNTechCompany Name - PeopleNTech

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Mountain View, California, USA

Contract, Third Party

Position: Senior Design Verification Engineer Location: Mountainview, California Experience: 7 to 12 years What candidate will Be Doing: Strong expertise along-with complex SoC/IP debug is mustAt-least 5+ years of experience in System Verilog HVL and C/C++.AMBA AXI bus along-with ARM or C based processorBi-frost/Processor based C and SV/UVM mix Verification. What we are looking for: A bachelor s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in

Design Verification Engineer (GPU)Job Title - Design Verification Engineer (GPU)

BayOne SolutionsCompany Name - BayOne Solutions

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San Jose, California, USA

Contract

Job Title - Design Verification Engineer (GPU) Duration 9 + Month (With the possibility of extension) Location:- San Jose (Onsite) Pay Rate :- $100/hr. - 120/hr. on w2 Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including th

Design Verification EngineerJob Title - Design Verification Engineer

Avance ConsultingCompany Name - Avance Consulting

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Austin, Texas, USA

Full-time

Job Description <>Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve

Design Verification EngineerJob Title - Design Verification Engineer

LeadStack, Inc.Company Name - LeadStack, Inc.

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No location provided

Full-time, Contract

Lead Stack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world. TITLE: Design Verification Engineer LOCATION: San Jose CA/ Austin TX DURATION: 5+ Months with possible extension Rate: $90-$110/hr on W2 Job Descriptio

Design Verification EngineerJob Title - Design Verification Engineer

Nityo Infotech CorporationCompany Name - Nityo Infotech Corporation

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Remote

Third Party, Contract

Design Verification Engineer Location: Santa Clara, CA/ Remote Mandatory Good DV Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or pythonExperience with Make, Yaml & Json file systems.Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis).Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows.Experience with flow optimizations such as Grey/B

Design Verification EngineerJob Title - Design Verification Engineer

AdientOne LLCCompany Name - AdientOne LLC

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Massachusetts, USA

Contract

Role: Design Verification Engineer Location: Boxborough MA 01719 | Hybrid Duration: 7 months Job Description: Collaborate with team to verify complex IP blocks. Develop and execute tests. Debug issues related to functionality, performance, and power. Work on functional and/or code coverage closure. Requirements: Proven experience working in UVM and constrained-random simulation environments. Strong knowledge of System Verilog, Verilog, C/C++, and scripting languages. Familiarity with 3D pipelin

Design Verification Engineer (GPU)Job Title - Design Verification Engineer (GPU)

West Coast Consulting LLCCompany Name - West Coast Consulting LLC

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Texas, USA

Contract

Job Description Austin, TX or San Jose, CA Onsite Description: Position Requirements: Role and Responsibilities: Key responsibilities include Work with architects and designers to build verification environments and test plans Craft functional verification coverage strategy to ensure complete test suite implementation Develop assertions and checks to optimize isolation time and produce meaningful failing signatures Analyze failing tests to root cause along, working with RTL and reference modeli

FPGA Design Verification EngineerJob Title - FPGA Design Verification Engineer

DBA Web TechnologiesCompany Name - DBA Web Technologies

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Dedham, Massachusetts, USA

Full-time

FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA7+ to 10 years of experience POSITION: FPGA Design Verification Engineer (OVM - UVM design verification, FPGA - ASIC design, bash, csh, Perl, TCL, Python, VHDL, Xilinx FPGA & Questa) in Dedham, MA SECURITY CLEARANCE: Must be able to obtain Secret Security Clearance (ship is Required) LOCATION: Dedham, MA (onsite) DURATION: Full-Time Positio

Mixed-Signal Design Verification EngineerJob Title - Mixed-Signal Design Verification Engineer

Talent Junction, LLC.Company Name - Talent Junction, LLC.

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San Jose, California, USA

Third Party, Contract

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

Design Verification Engineer- Remote- USAJob Title - Design Verification Engineer- Remote- USA

Yochana IT SolutionsCompany Name - Yochana IT Solutions

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Contract, Third Party

Good DV Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows. Experience with flow optimizations such as Grey/Black-boxing techniques Good at communicating requirements/issues wit

System IP Design Verification EngineerJob Title - System IP Design Verification Engineer

West Coast Consulting LLCCompany Name - West Coast Consulting LLC

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California, USA

Contract

Job Description ONSITE - San Jose, CA or Austin, TX Summary We are currently looking for exceptional hardware verification engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. System IP team develops proprietary coherent interconnect and memory controller IPs deployed in many high-volume products. Job Description As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verificat

Design Verification EngineerJob Title - Design Verification Engineer

Yoh - A Day & Zimmerman CompanyCompany Name - Yoh - A Day & Zimmerman Company

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Remote or Santa Clara, California, USA

Full-time

Design Verification Engineer Scope: Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams. Develop detailed block-level design specifications and plans for a high-performance IO Subsystem. Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers. Develop and optimize the IO subsystem design to ensure functionality and performance are in a

ASIC FPGA Design and Verification Engineer - (Experienced, Lead, or Senior) - MTVJob Title - ASIC FPGA Design and Verification Engineer - (Experienced, Lead, or Senior) - MTV

Boeing CompanyCompany Name - Boeing Company

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Mountain View, California, USA

Full-time

ASIC FPGA Design and Verification Engineer - (Experienced, Lead, or Senior) - MTV Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers (Experienced, Lead, or Senior) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products; ASICs and FPGAs in Mountain View, CA. From complex digitally beamformed phased arrays for constellation satellite programs to c

System Verilog UVM Design Verification Test EngineerJob Title - System Verilog UVM Design Verification Test Engineer

U.S. Tech Solutions Inc.Company Name - U.S. Tech Solutions Inc.

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Goleta, California, USA

Contract

Job Description: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data. Responsibilities: UVM/python test development for driving VIPs and other stimulus driversGeneration of test components such as monitors, scoreboards and python modelsCoverage closure and GLS bringup and testing Experience: 6+ years of experience with verification methodologies

FPGA Design and Verification EngineerJob Title - FPGA Design and Verification Engineer

Lockheed Martin CorporationCompany Name - Lockheed Martin Corporation

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Orlando, Florida, USA

Full-time

Job Description You will be a FPGA Design & Verification Engineer at Lockheed Martin, responsible for designing, simulating, and integrating Field-Programmable Gate Arrays (FPGAs) to design and develop Advanced EO/IR Fire Control system. Our team is looking for a talented engineer to join our team and support the development of cutting-edge technologies. What You Will Be Doing As a FPGA Design & Verification Engineer for Advance Program area, you will be responsible for capturing and deriving

Design Verification EngineerJob Title - Design Verification Engineer

JConnect IncCompany Name - JConnect Inc

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San Jose, California, USA

Full-time

Role: Design Verification Engineers (SoC-5, PCIe-5)Location: Bay AreaSalary: 160-240k (DOE) Free health insurancePTOs: 10 Business days (Including sick leaves) Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium) Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from speci

Hardware Test EngineerJob Title - Hardware Test Engineer

MethodHubCompany Name - MethodHub

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Morrisville, North Carolina, USA

Third Party, Contract

Lead Engineer -1 HW Test Engineer -1 Location: Morrisville, NC-USA Duration: 6+ months Lead: 12+ years of exp. In testing efforts of Lenovo server platforms across Software, Hardware, and Firmware areas adherent to Lenovo's PRR, Test cases, SOP, Test plans and bug reporting guidelines. Junior: 3+ years of exp. in testing efforts of Lenovo server platforms across Software, Hardware, and Firmware areas adherent to Lenovo's PRR, Test cases, SOP, Test plans and bug reporting guidelines. Job Descrip