Design Verification Engineer jobs

Sunnyvale, California

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11d ago

Are you interested in working with the World s leading AI-powered Quality Engineering Company? Ready to advance your career, team up with global thought leaders across industries and make a difference every day? Join us at Qualitest! We are looking for a Design Verification Engineer to join our growing team in Sunnyvale, CA United States! Job Description: Ensure the functional correctness, performance, and adherence to specifications for complex digital ASIC Core/IP designs. This role focuses on

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Full-time

$110,000 - $130,000

Senior Design Verification Engineer

Sunnyvale, California

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12d ago

Qualitest seeking an experienced Design Verification Engineer to ensure the functional correctness, performance, and spec compliance of complex digital ASIC Core/IP designs. This role involves deep, unit-level, and core-level verification, requiring strong technical expertise and the ability to drive verification independently. Location: Sunnyvale, CA Onsite, Full-Time (5 days/week) Key Responsibilities Plan: Develop detailed verification plans derived from micro-architecture and design specific

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Full-time

Depends on Experience

FPGA Design Verification Engineer- VLSI

Santa Clara, California

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3d ago

Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead II - VLSILocation: Santa Clara, CA . The Opportunity: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team, working on state of the art technologies. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification pla

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Contract, Third Party

$55 - $60

Senior Design Verification Engineer

Sunnyvale, California

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Today

This Jobot Job is hosted by: Holly Leahy Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $150,000 - $200,000 per year A bit about us: We are seeking a dedicated and detail-oriented Quality Technician to join our team. As a Quality Technician, you will play a critical role in ensuring the highest standards of quality in the manufacturing and assembly of cutting-edge electronics and components. This position will require you to collaborate clo

Full-time

USD 150,000.00 - 200,000.00 per year

Design Verification Engineer - Onsite

Austin, Texas

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26d ago

Title: Design Verification Engineer Onsite Mandatory skills: IO, PHY verification,IP verification, UVM, SystemVerilog, testbenches, tests,verification plan, Lead Formal verification, RTL verification,Comprehend AMS, Firmware, design spec, DV plan,Product Performance, Power issues debug, functional issues debug, resolution,Firmware Description: THE ROLE: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driv

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Contract

Depends on Experience

Design Verification Engineer

Redmond, Washington

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Today

Job#: 3013469 Job Description: Title: Design Verification Engineer Location: 100% Remote Benefit if Local to Seattle, WA Type: Contract Benefits: Medical Insurance, PTO, Holiday Pay, Sick Leave, 401K and more. About the Role We are seeking a highly skilled Design Verification Engineer with expertise in hardware verification and emulation. The ideal candidate will have hands-on experience with Verilog, SystemVerilog, UVM, and waveform debugging, as well as proficiency in writing RTL and testb

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Full-time

Design Verification Engineer - Verification Lead UVM / System Verilog / RTL Verification

Austin, Texas

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Yesterday

Job Title: Verification Lead UVM / System Verilog / RTL Verification Location: 100% Onsite Austin, TX 12+ Months Contract Top Must-Have Skills: UVM System Verilog RTL Verification Role Overview: We are seeking a seasoned Verification Lead with expertise or strong interest in IO/PHY verification. The ideal candidate will have a proven track record in IP verification, UVM, and SystemVerilog, with the ability to lead Design Verification (DV) teams and collaborate with world-class design and engi

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Third Party, Contract

$0.00/-

FPGA/Design Verification Engineer

Mountain View, California

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5d ago

Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite) Duration: 12%2B Months Job Description : Strong understanding of FPGA design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS). Knowledge of code coverage and functional coverage analysis. Excellent debugging and problem-solving skills. Strong communication and collaboration skills. Requi

Third Party

Hardware/FPGA/Design Verification Engineer (Mountain View, CA)

Mountain View, California

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5d ago

Job Title: Hardware/FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite)Duration: 12+ Months Job Description Strong understanding of FPGA design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS). Knowledge of code coverage and functional coverage analysis. Excellent debugging and problem-solving skills. Strong communication and collaboration skills.

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Contract

Depends on Experience

Design Verification Engineer

Remote

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3d ago

Key Responsibilities: Develop and maintain SystemVerilog/UVM-based testbenches for complex digital designs.Create and execute detailed test plans covering directed and constrained-random scenarios.Apply Object-Oriented Design principles to build scalable and reusable verification components.Analyze and improve code coverage metrics to ensure thorough verification.Write and maintain scripts (e.g., Python, Perl, Tcl) to automate verification flows and data analysis.Understand and enhance existing

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Full-time

$80 - $100

Senior Design Verification Engineer

Santa Clara, California

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11d ago

Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in IP and subsystemlevel verification using SystemVerilog and UVM. The engineer will own verification of complex digital IPs/subsystems, drive coverage closure, and collaborate closely with RTL, architecture, and validation teams to deliver highquality silicon. Key responsibilities - Own verification of one or more IPs or subsystems (e.g., interconnect, memory, I/O, compute blocks) from testplan to coverage cl

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Full-time

Depends on Experience

Senior Design Verification Engineer

Santa Clara, California

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30+d ago

Urgent Opening:DesignVerificationEngineer Job Title:DesignVerificationEngineer Experience: 10+ years Location: San Jose, CA (or other US locations) Job Type: Full-time/Contract KeyRequirements: - Experience working on Subsystems on a Chip (SoC) - Strong debugging skills to identify and resolve complex issues - Proficiency in scripting languages like C or Perl - Experience withDesignVerificationmethodologies and tools Responsibilities: - Develop and executeverificationplans for digitaldesi

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Contract

120 - 140

Design Verification Lead / RTL Engineer

Sunnyvale, California

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Today

We do have multiple open roles for RTL Engineer and Design Verification Lead in Sunnyvale, CA. Please find the JD and details below, and let us know if you interested / looking for new job. Location: Sunnyvale, CA or Mountain View, CA (on-site) Start Date: ASAP Role: RTL Engineer Open Positions: 6 Role Overview We are urgently seeking experienced RTL Engineers to join our team. The selected candidates will be responsible for developing and executing verification plans, building robust verificati

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Full-time

$125,000 - $175,000

RTL Design & Verification/Power Engineer

Sunnyvale, California

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25d ago

A client of Innova Solutions is immediately hiring for a RTL Design & Verification/Power Engineer role. Position type: Fulltime Location: Sunnyvale CA -Onsite As a RTL Design & Verification/Power Engineer, you will be need to have: Job description: Experience in design with power analysis experience.Verification engineers with power aware verification or low power design verification experience.ASIC/SOC power engineers with experience on tools like PTPX / RTL-A.RTL Design and Verification with

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Full-time

$145,000 - $155,000

Design Verification RISC-V CPU Development

Remote

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3d ago

Design Verification Engineer RISC-V CPU Development Are you passionate about cutting-edge CPU architecture and ready to take your verification skills to the next level? We re partnering with a global leader in RISC-V processor design to find talented Design Verification Engineers to join their high-impact VLSI team. You ll work alongside seasoned architects and engineers to verify next-generation RISC-V CPU cores, develop test benches from the ground up, and help shape the future of custom CPU I

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Full-time

Depends on Experience

SOC Core Data Path Design Verification Engineer

Boxborough, Massachusetts

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 149,800.00 per year

Staff CAD Design Verification Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm is a global leader in wireless technology, driving innovation and shaping the future of connectivity. We are looking for talented and motivated individuals to join our team in San Diego, to contribute to cutting-edge projects and help us continue to lead the industry. Role Overview: As a CAD Engineer specializing in design verification (DV), you will play a crucia

Full-time

USD 140,000.00 - 210,000.00 per year

AI/ML Design Verification Methodology Lead Engineer

Santa Clara, California

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Today

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a AI/ML Design Verification Methodology Lead, will involve in developing and implementing verification strategies, methodologies, and environments to ensure the functionality, performance, and robustness of variety of Qualcomm WIFI, connectivity and IOT devices architectures. The successful candidate will also lead a team of verification engineers and collaborate closely with

Full-time

USD 176,300.00 - 264,500.00 per year

Principal Engineer, SOC Design Verification

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 214,060.00 - 341,940.00 per year

Principal Engineer, Design Verification

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be

Full-time

USD 146,850.00 - 220,000.00 per year

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Design Verification Engineer jobs