Perl jobs in California

Hybrid in Livermore, California

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Today

Job Title: Senior Software Engineer Python/Perl, Django & Oracle Job Description: We are seeking a Senior Software Engineer to support and maintain the Environmental Information Management System (TEIMS) application suite used by Environmental, Safety and Health (ESH) and Environmental Restoration Department (ERD) teams. This role focuses on troubleshooting, break/fix support, bug fixes, and ongoing maintenance of existing web applications. The engineer will work with business stakeholders and t

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Contract, Third Party

Depends on Experience

Senior RTL / STA Engineer

San Jose, California

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Today

Hi Greetings from Envision, I Hope you are doing Well. Position: Senior RTL / STA Engineer Location: San Jose, California (on-site preferred), USA Duration: Contract of 1year Visa: Any Visa with valid Employment Authorization. No.of Positions: 1 Role Overview ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows.. Candidates with at least 8 years

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Contract

Depends on Experience

Senior Backend Engineer – Cloud Infrastructure

Remote

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Today

Senior Backend Engineer Cloud Infrastructure Location: Remote Job Description: Experience in backend cloud infrastructure development.Language Proficiency: Strong proficiency in Perl (legacy services) along with Go and Python.System Programming: Deep understanding of Linux OS internals, process management, memory optimization, and RESTful APIs.Hardware Awareness: Knowledge of ARM64 architecture, CPU affinity, and NUMA memory allocation.Virtualization: Experience working with VM lifecycle manage

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Contract

60 - 65

RTL/STA Engineer

San Jose, California

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7d ago

Position: Senior RTL / STA Engineer Location: San Jose, California (on-site preferred), USA Role Overview Ciscos ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. The preferred work location is Ciscos San Jose campus. Candidates with at least 8 years of relevant experience are preferred; candidates with somewhat less experience may be consider

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Full-time, Third Party

0 - 0

DFT MBIST Staff Engineer

Remote

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7d ago

Position: DFT MBIST Staff Engineer Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for c

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Full-time, Third Party

0 - 0

Orchestrator - Sr Engineer (W2-Requirement)

Remote

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4d ago

Role: Orchestrator - Sr Engineer (W2-Requirement) Location: Remote Duration: Long term Job Description: Experience in backend cloud infrastructure development. Language Proficiency: Strong proficiency in Perl (legacy services) along with Go and Python. System Programming: Deep understanding of Linux OS internals, process management, memory optimization, and RESTful APIs. Hardware Awareness: Knowledge of ARM64 architecture, CPU affinity, and NUMA memory allocation. Virtualization: Experience wor

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Contract

Depends on Experience

ECAD Application Engineer

Sunnyvale, California

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5d ago

Maintain, support, and enhance Cadence applications (OrCAD, Allegro, System Capture, Pulse PDM). Develop custom features, extensions, and automation workflows for Cadence tools. Build automation scripts using SKILL, Tcl, Python, Perl, and Unix Shell. Integrate AI/ML and LLM capabilities into ECAD design, review, and optimization workflows. Develop and support PDM/PLM integrations and ECAD data management processes. Troubleshoot EDA tools, installations, licensing, and system interoperability iss

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Contract

65 - 70

Senior Software Engineer

Livermore, California

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14d ago

Job Description We have an opening for aSenior Software Engineersupporting the Environmental Information Management System (TEIMS) application suite used by the Environment, Safety and Health (ESH) Directorate and the Environmental Restoration Department (ERD). As a senior software engineer, you will play a vital role in keeping LLNL employees and our environment safe. You will be responsible for performing break/fix support of applications within TEIMS used to support operations and environment

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Contract

Depends on Experience

Design Verification Engineer

San Jose, California

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6d ago

We are seeking Design Verification Engineer with exposure on Developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems) Key Skill: SV/UVM, PCIe/Ethernet/HBM What You'll Be Doing: Strong in SV/UVM scale test bench AXI expertise, NOC/Crossbar, Performance Regression/Triage and coverage closure Need asap Program has already started and is in execution Ability to work on Amazon tools, flows, methodology. Work is in start-up mode

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Third Party, Contract

Depends on Experience

Product Engineer II, Conformal

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This opportunity is for a Product Engineer working with the Conformal Products. You will be part of a highly efficient and independently-minded team of engineering professionals focused on our top customer's success. You will also be working closely with R&D to help deliver new product features, enhancements, and solutions. Must be able to work with strict deadlines, provide systematic

Full-time

USD 105,000.00 - 195,000.00 per year

DFT MBIST Staff Engineer

Remote

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Today

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Senior RTL / STA Engineer

San Jose, California

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3d ago

Position: Senior RTL / STA Engineer Location: San Jose, California (on-site preferred) Duration:12+ months No.of Positions: 1 Role Overview Ciscos ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. Key Responsibilities Develop, review, debug, and verify timing constraints for ASIC designs. Contribute to RTL design and collaborate with design,

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Contract

Depends on Experience

Product Engineering Architect (Computational Electromagnetics & Signal/Power Integrity)

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position responsibilities include: Drive key customer engagements in cooperation with local/international Field Applications teamInterface with R&D team to drive and influence product development to fulfill customer requirementsManage beta programs, author documentation and track customer issuesTravel, including international travel, may be required Position requirements: It is preferr

Full-time

USD 185,500.00 - 344,500.00 per year

Support Engineer Staff

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Services Group, Engineering Services Group > Support Engineering General Summary: Qualcomm's Emulation Team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC. The Emulation team works closely with architects, designers, verification engineers, software engineers, and customers. The team is currently seeking a candidate for emulation infrastructure and automation support engineer.

Full-time

USD 49.45 - 74.15 per hour

ASIC Power Engineer

Irvine, California

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Today

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering teams. In this highly visible role, you will be at the center of low power architecture, power modeling and

Full-time

CPU Low Power RTL Design Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this role, you will work with chip architects to conceive of the micro-architecture and help with architecture/product definition through early involvement in the product life cycle. Required for this Role: MS degree in Computer or Electrical Engineering or BS degree

Full-time

USD 124,300.00 - 186,500.00 per year

Senior Design Verification Engineer

San Francisco, California

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4d ago

Senior Design Verification Engineer Location: Bay Area, CA (Complete Onsite) Experience: 5+ years (Relevant) Key Skill: SV/UVM, AXI expertise, NOC/Crossbar, Performance What You'll Be Doing: Strong in SV/UVM scale test bench AXI expertise, NOC/Crossbar, Performance Regression/Triage and coverage closure Need asap Program has already started and is in execution ARM CPU_SS (Cortex, Neon), Ability to work with Firmware team, Emulation is plus Coresight Debug Arch, DMA, NIC (AXI), C/SV mixe

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Contract

Depends on Experience

RFIC Layout Engineer

San Francisco, California

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Today

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references. Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing

Full-time

DFT MBIST Staff Engineer

Remote

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3d ago

Position: DFT MBIST Staff Engineer Location Remote (must be aligned with PST time zone) Duration: 12 months. No.of Positions: 1 Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, an

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Contract

Depends on Experience

Design For Test (DFT) Engineer

San Jose, California

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Today

Job Description Onsite San Jose - 5 days a week Description The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets. JOB RESPONSIBILITIES: Experience with memory BIST - Siemens Tessent Flow Experience with gate-level simulation and si

Contract

Perl jobs in California, USA