UVM jobs in California

Hybrid in Santa Clara, California

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Today

FPGA Verification Engineer Location Santa Clara, CA Onsite Requirement - Y/N- Y Number of days onsite 5 Days Mandatory Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA Skill 2 5 +Years of Exp in UVM Skill 2 5 +Years of Exp in System Verlilog Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionalit

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Contract, Third Party

$60 - $70

SystemVerilog/UVM Design Verification Test Engineer

Hybrid in Goleta, California

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8d ago

Job Description: We are seeking a highly skilled and meticulous SystemVerilog/UVM Design Verification Test Engineer to play a crucial role in validating our complex System-on-Chip (SOC) and Integrated Circuit (IC) designs. This role requires expert-level proficiency in SystemVerilog and UVM, a strong understanding of processor architectures, and high-speed protocols. Responsibilities: Architect, develop, and maintain advanced verification environments (Testbenches) using UVM and SystemVerilog

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Contract

$70 - $100

Formal Verification Engineer

California City, California

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26d ago

Job Title: Formal Verification EngineerLocation: Bay Area, CA.Experience: 7+ Years. Work Authorizations: s and s. Job SummaryWe are seeking a highly skilled and motivated Formal Verification Engineer to join our hardware design and verification team. In this role, you will be responsible for applying formal methods to verify the correctness of digital designs, ensuring they meet functional specifications and industry standards. You will collaborate closely with design, verification, and architec

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Contract

$85 - $120

FPGA Verification Engineer

Santa Clara, California

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5d ago

FPGA Verification EngineerSanta Clara, CA - Onsite Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products. Key Responsibilit

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Contract, Third Party

Depends on Experience

FPGA Validation Lead Engineer

Santa Clara, California

•

Yesterday

We are looking for an experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop and execute verification plans, debug issues, and ensure high-quality, reliable products. Responsibilities: .Develop and maintain test benches using UVM/SystemVerilog. .Write and debug test cases for functional and performance validation. .Identify and resolve design issues in collaboration with engineering teams. .Participate in design reviews and contribute to verification strategy. .S

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Full-time

Depends on Experience

FPGA Verification Engineer

Santa Clara, California

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7d ago

Role: FPGA Verification Engineer Duration: 12 Months Location: Santa Clara, CA Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our

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Third Party, Contract

Depends on Experience

FPGA Verification Engineer

Santa Clara, California

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6d ago

Role: FPGA Verification Engineer Location: Santa Clara, CA (Fully onsite) Duration: 12+ Months Must have: FPGAExp in UVMExp in System Verlilog Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify

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Contract, Third Party

Depends on Experience

Verification Engineer - Hybrid

Hybrid in San Jose, California

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15d ago

Title: Verification Engineer - Hybrid Description: JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsi

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Contract

$102.14 - $107.14

Design Verification Engineer, FPGA

Sunnyvale, California

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16d ago

Job Responsibilities: Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVMDevelop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functionsCollect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;Enhance your leadership skills while contributing to a dynamic DV teamCreate reusable Verification IP

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Contract

$50 - $80

Design Verification Engineer

Hybrid in Sunnyvale, California

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7d ago

3+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.3+ years' experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.Experience in architecting and im

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Contract

$80 - $90

FPGA Verification Engineer

Mountain View, California

•

Today

FPGA Verification Engineer Santa Clara, CAMandatory Areas Must Have Skills Skill 1 - 8 + Years of in FPGA Skill 2 - 5 +Years of Exp in UVM Skill 2 - 5 +Years of Exp in System VerlilogJob Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop a

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Full-time, Contract

BASED ON EXPERIENCE

Design Verification Engineer

Sunnyvale, California

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28d ago

A client of Innova Solutions is immediately hiring for a Design Verification Engineer. Position type: Fulltime Location: Sunnyvale CA-Onsite As a Design Verification Engineer, you will be responsible for: Job description: Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirements.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level

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Full-time

$160,000 - $170,000

Design Verification Engineer

Remote or California

•

Today

Skills: Standard DV skills. Candidate must have experience with processor based C -tests. SV & UVM (TB and test development, debug) Functional & code coverage Formal Verification (connectivity checks) CDC verification Emulation/Post Silicon Platform Gate Level Simulation Understanding CPU based Flow (Specifically on ARM processor based) - interconnects, boot, caches, MMU, interrupts Processor based C test development and debug Protocol knowledge (AXI, APB, CHI, PCIe, HBM, DDR etc.) SoC Architec

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Third Party, Contract

FPGA Verification Engineer

Santa Clara, California

•

Today

Role: FPGA Verification Engineer Location: Santa Clara, CA (Onsite from Day 1) Contract Must Have Skills: FPGA Verification Engineer Skill 1 8 + Years of in FPGA Skill 2 5 +Years of Exp in UVM Skill 2 5 +Years of Exp in System Verlilog Key Responsibilities: Develop and execute comprehensive verification plans for FPGA designs. Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog). Write and debug test cases to verify functionality, perf

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Contract, Third Party

Design Verification Engineer

Remote

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5d ago

Job Title:Design Verification Engineer Location:Remote Experience Level:7+ Years Job Description: We are seeking a skilledDesign Verification Engineerwith strong expertise inSystem Verilog (SV)andUVMmethodologies to join our team. The ideal candidate will have hands-on experience in developing, updating, and debuggingverification testbenches, with the ability to integrateVerification IPs (VIPs)orDesign IPsinto the verification environment. Responsibilities: Develop, enhance, and debug System Ver

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Third Party, Contract

80 - 100

Verification Lead FPGA

San Carlos, California

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7d ago

We are looking for an experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop and execute verification plans, debug issues, and ensure high-quality, reliable products. Responsibilities: Develop and maintain test benches using UVM/SystemVerilog.Write and debug test cases for functional and performance validation.Identify and resolve design issues in collaboration with engineering teams.Participate in design reviews and contribute to verification strategy.Stay curre

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Full-time

Depends on Experience

IC Verification Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology Build pseudo-rand

Full-time

USD 120,000.00 - 192,000.00 per year

Pre-Silicon Digital Verification Engineer

Cupertino, California

•

Today

Join an accomplished team at Apple developing custom integrated circuits for Apple's existing and future product lines. As a member of our PMU ASIC team, you will be responsible for verifying complex digital IP's. You will work with the product teams, system architects, and digital designers, in refining microarchitecture specifications. You will use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions in your blocks. You will

Full-time

USD 147,400.00 - 272,100.00 per year

RTL Design Engineer/Architect

Hybrid in Santa Clara, California

•

Today

Position: RTL Architect SERDES Location: USA (Onsite/Hybrid) Austin , TX & Santa Clara, CA Experience Required: 8+ years Notice Period: Immediate Key Responsibilities Define and own the RTLarchitecturefor high-speed and many lanes SERDES IPs.Lead RTLdesign, coding, and integrationof SERDES blocks.Collaborate with analog, verification, PD, and validation teamsto ensure seamless integration and successful silicon bring-up.Drive micro-architecture development, specification reviews, and design doc

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Full-time

Depends on Experience

Sr. ASIC/SOC Verification Engineer (Silicon Engineering)

Sunnyvale, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC/SOC VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink i

Full-time

USD 170,000.00 - 230,000.00 per year

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UVM jobs in California, USA