UVM jobs in South San Francisco, CA

Senior Emulation/Verification Engineer In Bay Area, CA || Hybrid Role

Hybrid in Menlo Park, California

•

Today

Role: Senior Emulation/Verification EngineerDuration: Long TermLocation: Bay Area, CA || Hybrid Role Job Description-: We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

Easy Apply

Contract

Depends on Experience

Verification Engineer

Sunnyvale, California

•

5d ago

Hello, Hope you are doing well. Title: ARM IP Verification Engineer Location: Sunnyvale, CA Are you passionate about building robust verification environments for next-gen silicon? We are looking for an experienced ARM IP-Level Verification Engineer to join our team in Sunnyvale, CA. If you thrive on architecting complex UVM testbenches, driving coverage closure, and developing custom VIP from the ground up, we want to hear from you. Key Focus Areas: SystemVerilog & UVM mastery Custom VIP de

Easy Apply

Contract

50 - 60

Emulation Verification Engineer

San Francisco, California

•

Today

Imagine what you could at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengt

Full-time

Design Engineer

Sunnyvale, California

•

10d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

Easy Apply

Third Party, Contract

$82 - $85

Digital Verification Engineer

South San Francisco, California

•

Today

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Job Description & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team. This position offers

Full-time

USD 131,000.00 - 243,000.00 per year

Design Engineer III

Sunnyvale, California

•

Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

Senior ASIC Verification Engineer

San Francisco, California

•

Today

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software developmen

Full-time

Core Engineering - Design Engineer III

Sunnyvale, California

•

Today

Job#: 3045115 Job Description: Core Engineering - Design Engineer Location: Sunnyvale, California (Partial Remote) 3 days / week onsite Compensation: $70- $80 Hourly Role Overview This position is for a Design Verification engineer focused on wearables silicon accelerator IPs. The role involves testbench development, coverage-driven verification, RTL debug, and power and performance measurement. The successful candidate will work with a small team to build and run testbenches, analyze cove

Easy Apply

Full-time

$70 - $80 per hour

Principal Verification Engineer

Mountain View, California

•

Today

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and complian

Full-time

USD 142,800.00 - 274,800.00 per year

Senior Verification Engineer

Mountain View, California

•

Today

Full-time

USD 119,800.00 - 234,700.00 per year

Design Verification Engineer

Remote

•

5d ago

Hi - Full Time Role Job Title: Design Verification Engineer -Performance Modelling Location : Remote USA Strong understanding of SV and UVM and good debugging skills.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely wi

Easy Apply

Full-time

Depends on Experience

Design Verification Engineer

Remote

•

6d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

Easy Apply

Contract

Depends on Experience

Post-Silicon Systems Software Validation Engineer

Remote or California

•

Today

Position: Post-Silicon Systems Software Validation Engineer Job Description: - Strong programming skills (Python, Lua, C/C++, Rust, Go, etc) - A solid understanding of computer architecture and chip/system validation methodologies - Firmware testing and/or development (BIOS, BMC, drivers) - Domain expertise in any of these areas: PCIe, HBM, GPUs, neural networks, ML HW architecture - Knowledge of the full validation lifecycle from RTL simulation (SystemVerilog/UVM, VCS, Questa, Xcelium) and emu

Full-time

USD 87,400.00 - 165,000.00 per year

Mixed-Signal Verification Engineer

San Francisco, California

•

Today

Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level. All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation

Full-time

Verification Engineer in CA and TX

San Francisco, California

•

Today

Hi, I hope all is well. I am doing a search for a client who has an urgent requirement for a network administrator contract opportunity. The job description is listed below. If this is something you are interested in, please call me ASAP at . please mail me your updated resume in Word format, availability, contact details, and hourly rate as per the hiring policy of our client. ASIC Verification Engineer About the role: PCIe Protocol IP Verification Expert: Consulting & Turnkey projec

Easy Apply

Third Party, Contract

Depends on Experience

Design Verification Engineer III

Sunnyvale, California

•

Today

Job Title: Design Verification Engineer Location: Sunnyvale, CA (Onsite 3 days/week) Duration: Contract - 6 months, extension TBD Pay Range: $60/hr - $65.32/hr (W2). Job ID: 407927 About BCforward BCforward is a leading global IT consulting and workforce solutions firm providing services and support to Fortune 500 and government clients. Founded in 1998, BCforward has grown with our customers needs into a full-service business solutions provider. With delivery centers and offices across No

Easy Apply

Contract

$65.32 - $65.32 per hour

Principal Product Engineer - Virtual Protocols

Remote or San Jose, California

•

Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Business Overview Deliver Emulation and Prototyping assisted verification products using virtualization (SW) technologies to accelerate and shift left SW-driven pre-silicon verification of advanced SoC designs. Job Description This Principal Product Engineer position is with the Virtual Protocols Product Engineering Team, responsible for the successful field readiness and customer dep

Full-time

USD 136,500.00 - 253,500.00 per year

Emulation Engineer

Remote or California

•

Today

Senior Emulation Engineer Location: San Jose, CA (Remote) Experience: 10+ Years We are hiring an experienced Senior Emulation Engineer with strong expertise in Siemens Veloce, Cadence Palladium, or Synopsys ZeBu. Required Skills: Hands-on experience with Veloce, Palladium, or ZeBu emulation platforms Experience with FPGA prototyping (HAPS, Protium, or proFPGA) Strong knowledge of PCIe, UCIe, LPDDR, and HBM Solid understanding of SoC architecture, RTL (Verilog/SystemVerilog), and digital des

Easy Apply

Full-time, Part-time, Contract, Third Party

Senior Solutions Architect (Embedded, IoT & Connected Devices)

Remote

•

26d ago

Senior Solutions Architect Semiconductor & Connected Devices Location: Bay Area, CA (Preferred) / Remote (USA) Employment Type: Full-Time Experience: 1520 Years About Innominds: Innominds is a leading Digital Engineering company that accelerates innovation for global enterprises by combining Product Engineering, AI, Data, Cloud, Connected Devices, Semiconductor Engineering, and Digital Transformation. We partner with Fortune 500 companies and technology innovators to build intelligent products

Easy Apply

Full-time

Depends on Experience

ASIC Verification Engineer

Hybrid in Burlingame, California

•

3d ago

Title: ASIC Verification Engineer (Python/Cocotb) Hybrid Role- 3 days onsite/2 days remote- (Burlingame, CA or Burlington, MA) Length of Contract: 6-9 months - Temp-to-Perm Hours: 40 hours per week Scope:Client needs someone to lead verification for complex SoC subsystems using Python-based frameworks (CocoTB Framework) with a focus on DSP validation and/or CPU subsystems, scalable test environments, and full verification closure through tapeout. Must haves: 8+ years inASIC/SoC digital verifi

Easy Apply

Contract

$80 - $90

UVM jobs in South San Francisco, CA, USA