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Job Title:Design Verification Engineer Location:Remote Experience Level:7+ Years Job Description: We are seeking a skilledDesign Verification Engineerwith strong expertise inSystem Verilog (SV)andUVMmethodologies to join our team. The ideal candidate will have hands-on experience in developing, updating, and debuggingverification testbenches, with the ability to integrateVerification IPs (VIPs)orDesign IPsinto the verification environment. Responsibilities: Develop, enhance, and debug System Ver
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80 - 100