jedec Jobs in boston, ma

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Senior Quality Manager

Infineon Technologies AG

Andover, Massachusetts, USA

Full-time

Job DescriptionThe role involves defining and implementing quality targets for multiphase and POL ICs and power modules based on customer and market requirements, while overseeing the entire product lifecycle to ensure quality criteria are met. It includes developing qualification strategies, managing product qualification, addressing customer needs,and handling product deviations and risk assessments in production.Additionally, the role focuses on deploying new quality tools, training colleague

Lead Semiconductor Reliability Engineer

RTX Corporation

Andover, Massachusetts, USA

Full-time

Date Posted: 2025-07-18 Country: United States of America Location: MA112: Andover MA 358 Lowell St Dukes 358 Lowell Street Dukes, Andover, MA, 01810 USA Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required.Security Clearance: DoD Clearance: Secret At Raytheon, the foundation of everything we do is rooted in our values and a higher calling - to help our nation and al

R&D Engineering, Sr Staff Engineer - 10360

Synopsys, Inc.

Boxborough, Massachusetts, USA

Full-time

Descriptions & Requirements Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candid

DV Engineers DDR (either IP or SoC level experience)- Remote

E-Solutions, Inc.

California, USA

Full-time, Contract, Third Party

Role: DV Engineers DDR (either IP or SoC level experience) Work Location: USA (Remote) Experience: 10+ Years Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own f