Verification engineer jobs

Santa Clara, California

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Today

ASIC Verification Engineer Santa Clara, CA 12 + Months $75 - $80/HR Role: Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random simulation. Must Have: 5-7 years experience, expert C/C++ in Linux, OOP/STL, and Verilog/SystemVerilog (Formal Verification / 7+ years preferred). Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one o

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Contract

$75 - $80 per hour

Principal ASIC Verification Engineer

San Jose, California

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Today

Principal ASIC Verification Engineer San Jose, CA 6 + Months $95 - $100/HR Role: Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random testing. Must Have: 10+ years experience, expert C/C++ in Linux environments, OOP/STL, debug tools (Gdb/Valgrind), and Verilog/SystemVerilog. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one

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$95 - $100 per hour

Formal Verification Engineer

Austin, Texas

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Today

Formal Verification Engineer Austin, TX 12 + Months Role: Lead design verification using formal tools and spec analysis. Must Have: VC Formal or JasperGold, SystemVerilog Assertions (SVA), and FPV applications. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing compan

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Senior ASIC Verification Engineer

San Jose, California

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Yesterday

We are looking for Senior ASIC Verification Engineer for our client in San Jose, CAJob Title: Senior ASIC Verification Engineer Job Location: San Jose, CA Job Type: Contract Pay Range: $104.47hr - $110.27hr Job Overview: The candidate will participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. As part of a team of design and verification engineers, the successful candidate will work closely with other team members to u

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Third Party, Contract

Depends on Experience

Test and Verification Engineer

Huntsville, Alabama

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Today

Job Number: R0246151 Test and Verification Engineer The Opportunity: Are you looking for an opportunity to combine your technical skills with big picture thinking to make an impact in space? You understand your customer's environment and how to develop the right systems for their mission. Your ability to translate real-world needs into technical specifications makes you an integral part of delivering a customer-focused engineering solution. As a systems engineer on our team, you'll have the cha

Full-time

USD 86,800.00 - 198,000.00 per year

Design Verification Engineer

San Jose, California

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Today

Client: Etched Design Verification Engineer 6 Openings Location: San Jose, CA & Austin, TX - onsite Please find the JD: Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ab

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Full-time, Third Party

Depends on Experience

SoC verification Engineer

Remote

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Today

Position : SoC verification Engineer Location : Remote Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.Testbench & Component Devel

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Contract

$70+

ASIC Verification Engineer

Carlsbad, California

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Today

RESPONSIBILITIES: Kforce is immediately seeking an experienced ASIC Verification Engineer to support our enterprise networking and cloud solutions customer based in Carlsbad, CA. Summary: We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. The ASIC Verification Engineer will work in a collaborative environment, participating in architectural decisions and verificat

Contract

$60 - $71 hourly

Field Verification Engineer

Edison, New Jersey

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Today

Role :-Field Verification Engineer Location -Midland Texas Job Type :- Full Time P&IDs and Plant experience Must JOB DESCRIPTION:- The Mechanical Engineer - Asset Management will be responsible for developing and maintaining asset information, equipment hierarchy, preventive maintenance programs, Bills of Materials (BoM), and reliability improvement initiatives for industrial facilities. The role involves supporting asset management systems such as Maximo, SAP PM, or other CMMS platforms to imp

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Full-time, Third Party

Depends on Experience

DFx Verification Engineer

Santa Clara, California

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Today

DFx Verification Engineer Location: - Santa Clara, CA (Onsite) Exp Range: - 5-20 Years of experience Long Term Contract (12 Months +) / Full Time Position JD Key Responsibilities Develop and execute verification plans for DFx features including: Scan (stuck-at, transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Create and maintain testbenches using SystemVerilog/UVM for DFx validation Verify: Scan chain integrity and connectivity T

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Full-time, Part-time, Contract, Third Party

FPGA Design/Verification Engineer

Owego, New York

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Today

Location: Owego, NY Salary: $70.00 USD Hourly - $80.00 USD Hourly Description: Role: Fpga Design/verification Engineer Location: (Hybrid) Employment type: contract Job Description: The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms. Experience

Contract

USD 70.00 - 80.00 per hour

ASIC Verification Engineer

Santa Clara, California

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Today

ASIC Verification Engineer Verification Engineer 3Location: Santa Clara, CA 95054 Contract: 12+ Months Candidate Pay: $75/HR on W2 Job OverviewWe are seeking an experienced ASIC Verification Engineer Verification Engineer 3 to join our semiconductor engineering team in Santa Clara, CA. The ideal candidate will have strong hands-on experience in block-level functional verification of complex CPU/GPU SoCs, with expertise in simulation, SystemVerilog, Verilog, and C/C++ development in a Linux env

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Contract

Depends on Experience

Systems Verification Engineer

Cedar Rapids, Iowa

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Yesterday

InfoWeb Systems, Inc. hasthe following requirement for our direct client, Collins Aerospace. All candidates must have GREAT COMMUNICATION skills and SOLID WORK EXPERIENCE. Location: ONSITE in Cedar Rapids, IA Duration: 6+ months # of positions: 5 (FIVE) Rate: $60-65/hr C2C Interview: Zoom Avionics Verification Engineer Description of duties: - You will perform design, requirements, validation, & verification tasks for MH-60M and MH-47G cockpit avionics for the US Army Special Operations Aviati

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Contract

Depends on Experience

Principal Verification Engineer

San Jose, California

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14d ago

Verification Lead / Principal Verification EngineerLocation:San Jose, CA |Experience:10+ Years Duration: Long TermOwn end-to-end verificationHands-on experience with AXI4 protocol verification and Memory Management.HBM verification experience is a strong plus.Lead and mentor verification engineers through tape-out and sign-off.

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Contract

80 - 90

Verification Engineer

Saratoga, California

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27d ago

Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field.Experience:A MINIMUM of8-15 years in ASIC verification in the area of data center networking.Verification Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power simulations, constrained random verification and test-plan documentat

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Full-time

150000 - 200,000

Mixed Signal Verification Engineer

San Jose, California

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Today

Job Title: "Mixed Signal Verification Engineer" Location: San Jose, CA (Onsite) Duration: Long Term Contract JOB RESPONSIBILITIES Creating AMS/DMS testbench for wireless RF and High Speed PHY. Working with RF/Analog design engineers for analog circuit models Support silicon bring-up and commercialization. REQUIRED SKILLS BS or BE minimum, 3+ year experiences Deep understanding of digital VLSI simulation flow Deep understanding of mixed-mode and analog simulation flow Experience with Verilog/Sys

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Contract

90 - 150

Verification Engineer

Hybrid in Santa Clara, California

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28d ago

Role: Verification Engineer Location: Santa Clara, CA & Contract Job Description: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test p

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Contract

Depends on Experience

Electronics Verification Engineer

New York, New York

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6d ago

Job Description: The Electronics Verification Engineer is responsible for validating and qualifying electronic hardware from prototype through production. On a day-to-day basis, this role involves hands-on board bring-up and bench testing using lab instrumentation (oscilloscopes, DMMs, power supplies, etc.), executing validation plans against design requirements, troubleshooting circuit-level failures, performing PCB rework, and capturing/analyzing test data. The engineer writes and maintains te

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Contract

Depends on Experience

SoC Verification Engineer

Remote

•

Yesterday

Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.Testbench & Component Development: Build and maintain verification components, t

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Contract, Third Party

60 - 70

Verification Engineer

Sunset Valley, Texas

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19d ago

Job Description:Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)Strong proficiency in System Verilog Assertions (SVA) and formal property specificationExperience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysisFamiliarity with scripting languages (TCL, Python, Perl) for flow automationExtensive experience in design verification with a strong focus on formal verificationExpertise in Syst

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Third Party, Contract

Depends on Experience