Search Jobs | Dice.com

Remote

•

5d ago

Job Description: Senior Clock Domain Crossing (CDC) Contractor to support our engineering team. This is a critical, focused on maintaining design integrity during a transition period. The ideal candidate will serve as a subject matter expert in CDC analysis and ASIC Design-for-Test (DFT) constraints. leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips Design & implement robust and reusable RTL with CDC/RDC considerations Spec compre

Easy Apply

Contract, Third Party

$100 - $110

Senior ASIC DFT CDC Constraints Eng

California

•

Yesterday

Hello Team, Please share the profiles for below requirement and kindly let me know if you any questions. Senior ASIC DFT CDC Constraints Eng Milpitas, CA - Remote Candidate can be based anywhere in US but willing to work in PST time zone. Skills Matrix No. of years of Exp CDC analysis ASIC Design DFT CDC(Clock Domain Crossing) RDC (Reset Domain Crossing) Static Timing Analysis SVA (SystemVerilog Assertions Job Description: Senior Clock Domain Crossing (CDC) Contractor to support our engineering

Third Party, Contract

$$65

DFT Engineer

San Jose, California

•

16d ago

Role :- Senior ASIC DFT CDC Constraints Eng Location :- San Jose, CA/Milpitas, CA (Remote) Type :- */W2 This is a highly specialised role at the intersection of Design for Test (DFT) architecture and clock domain crossing (CDC) constraint engineering. The successful candidate will own the SDC/SSTA constraint strategy that governs both functional timing closure and DFT scan-mode operation across a complex multi-clock SoC. You will work daily at the boundary where CDC violations manifest as sca

Easy Apply

Full-time, Third Party

Depends on Experience

Sr. ASIC DFT Engineer (Silicon)

Austin, Texas

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, California

•

Today

Full-time

USD 135,000.00 - 160,000.00 per year

Sr. ASIC DFT Engineer (Silicon)

Irvine, California

•

Today

Full-time

USD 125,000.00 - 150,000.00 per year

Lead ASIC DFT Engineer

Remote

•

10d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

Easy Apply

Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

2d ago

Job Title: Lead ASIC DFT Engineer Location: Remote Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal

Easy Apply

Third Party

Lead ASIC DFT Engineer

Remote

•

6d ago

Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical sil

Easy Apply

Third Party, Contract

$70 - $90

Lead ASIC DFT Engineer

Remote

•

4d ago

Job Description Role:Lead ASIC DFT Engineer Location: Remote(must be aligned with PST time zone) Role Summary We are seeking a highly experiencedLead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resoluti

Easy Apply

Full-time

70 - 75

Lead ASIC DFT Engineer

Remote

•

2d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Duration - Contract Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundar

Easy Apply

Third Party, Contract

$75 - $80

Sr DFT Engineer

Santa Clara, California

•

24d ago

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin

Easy Apply

Contract, Third Party

Depends on Experience

Applications Engineering, Sr Staff Engineer- 16949

Sunnyvale, California

•

Today

Descriptions & Requirements Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You A

Full-time

Integration Engineer

Santa Clara, California

•

Today

Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies

Full-time

Senior Product/Test Engineer

Santa Clara, California

•

5d ago

Required Qualifications BS in Electrical Engineering, Computer Engineering, or Computer Science with 510 years of experience; or MS/PhD with 35 years of experience. Background in ASIC or Custom Processor Product Engineering, Product Test Engineering, or Test Solutions Engineering. Strong experience with: Product characterization Data analysis Automated Test Equipment (ATE) Design for Test (DFT) Semiconductor manufacturing Yield analysis Reliability testing Quality engineering ASIC or processor d

Easy Apply

Full-time

60 - 65

Job Title: Senior Physical Design / STA Engineer - W2

California City, California

•

10d ago

Job Title: Senior Physical Design / STA EngineerLocation: Bay Area, CA / Austin, TX - CA 1st preferenceEmployment Type: Long-Term Contract (W2 Only) Position SummaryWe are seeking a Senior Physical Design / STA Engineer with strong hands-on experience in physical design and static timing analysis for advanced semiconductor projects. The ideal candidate will have expertise in timing closure, synthesis, place & route, and signoff activities for high-performance ASIC/SoC designs. ResponsibilitiesPe

Easy Apply

Contract, Third Party

Senior CDC Engineer

San Jose, California

•

4d ago

Senior CDC Manager San Jose, CA Experience: 10+ years Job Details: We are looking for a senior CDC (Clock Domain Crossing) Contractor based in the US. The contractor will work on ASIC DFT CDC constraints until our group can fill in the position. Interview will test understanding of CDC and Spyglass tool at a senior level. Contractor Requirements & Skills Skill set: Spyglass CDC / VC-Spyglass. CDC/RDC knowledge Top 3 responsibilities We are looking for a senior CDC Clock Domain Crossing Contracto

Contract, Third Party

Depends on Experience

Senior FPGA Engineer

Englewood, Colorado

•

Today

Company Description Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space. Job Description Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs. Candidate shall have experience with Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexi

Full-time

USD 130,000.00 - 185,000.00 per year

Lead ASIC DFT Engineer

No location provided

•

Today

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Any Visa Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-sil

Easy Apply

Contract

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Austin, Texas

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

Full-time

Filter Results

Job post features

Posted date

Work settings

Employment type

Distance

Employer type

Work authorization