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San Jose, California

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Today

We are looking for ASIC/RTL Design Engineer 2 for our client in San Jose, CA.Job Title: ASIC/RTL Design Engineer 2 Job Location: San Jose, CA Job Type: Contract Job Overview: Pay Range: $60/hr - $62/hr The position involves working on advanced digital CMOS processes and leading the design of state-of-the-art SoCs.Requirement/Must Have: Experience in SoC Architecture.Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing

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Contract, Third Party

Depends on Experience

ASIC RTL Design Engineer - Onsite

San Jose, California

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Today

Title: ASIC RTL Design Engineer - Onsite Mandatory skills: SoC Architecture, ASIC design flow, RTL coding, debugging, verification, supporting synthesis, timing closure, ARM cores, I/O standard interfaces, Ethernet, DDR, DMA, PCIE, SATA, internal IPs, digital CMOS processes, SoC design, Chip definition, Architecture development, modeling, micro-architectural specifications, micro-architectural specifications, logic implementation, emulation, debug Description: JOB DUTIES: The work will expose th

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Contract

57 - 62

ASIC/RTL Design Engineer

San Jose, California

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Today

Job Title: ASIC/RTL Design Engineer 2 Location: San Jose, CA Type: 12+ Months Contract Job Duties: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IP?s. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including Chip Definition, Architecture develop

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Contract

Depends on Experience

ASIC/SoC RTL Design Engineer

San Jose, California

•

Today

In-Person Interview Required! SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Design and develop advanced SoCs across architecture, RTL, and verification. Responsibilities: RTL design, verification, and debugging Support synthesis and timing closure Work with ARM cores, DDR, PCIe, Ethernet, and IP Collaborate with design and bring-up teams Qualifications: Experience in ASIC/SoC design and RTL coding Knowledge of ARM and standard I/O interfaces Dexian stands a

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Contract

$60 - $62.50 per hour

Integration RTL Design Engineer

San Jose, California

•

Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

ASIC / RTL Design Contractor

Remote

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12d ago

Location:REMOTEDuration: ~12 months (Immediate start through Q1 next year)Team Size: ~10 Engineers (Mix ofDesign & DV )Question from hiring manager on prior submital: Can you also check with the candidates on their recent hands-on experience with RTL design using SystemVerilog, & working on IPs with multiple clock domains?1. RTLDesignEngineerKey ResponsibilitiesOwn micro-architecture definition from high-level functional specificationsDevelop and implement RTL for complex digital blocksDrive dig

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Contract, Third Party

70 - 90

Senior Engineer, GPU RTL Design - Pixel Pipe

San Jose, California

•

Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 139,000.00 - 208,400.00 per year

Senior ASIC Design Engineer - Clocks IP

Santa Clara, California

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Today

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human

Full-time

USD 136,000.00 - 218,500.00 per year

Staff/Principal Engineer. ASIC Design Verification (DDR expert)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff/Principal ASIC SoC Design Verification Engineer - DDR expert (Technical role) Position Description: This is a position for Staff technical member of Micron's

Full-time

USD 168,000.00 - 336,000.00 per year

ASIC Physical Design Engineer

San Jose, California

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10d ago

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Great base pay, bonus, terrific benefits and exceptional 401k! he MissionStaffRight Associates is recruiting to identify a high-caliber ASICPhysical Design Engineer to spearhead the structural realization of next-generation System-on-Chip (So

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Full-time

170000 - 220000

Senior Engineer, RTL Design

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 138,000.00 - 206,000.00 per year

Staff Engineer, RTL Design

San Jose, California

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Today

Full-time

USD 163,000.00 - 253,000.00 per year

Staff Engineer, ASIC Design Verification

San Jose, California

•

Today

Full-time

USD 163,000.00 - 253,000.00 per year

DFT Engineer

San Jose, California

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4d ago

Role :- Senior ASIC DFT CDC Constraints Eng Location :- San Jose, CA/Milpitas, CA (Remote) Type :- */W2 This is a highly specialised role at the intersection of Design for Test (DFT) architecture and clock domain crossing (CDC) constraint engineering. The successful candidate will own the SDC/SSTA constraint strategy that governs both functional timing closure and DFT scan-mode operation across a complex multi-clock SoC. You will work daily at the boundary where CDC violations manifest as sca

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Full-time, Third Party

Depends on Experience

Lead ASIC DFT Engineer

San Jose, California

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Today

Title: Lead ASIC DFT Engineer Location: San Jose, CA - Onsite Type: Contract Job Description: Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Required Skills & QualificationsStrong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cad

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Contract

Depends on Experience

Senior ASIC Design Architect

San Jose, California

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10d ago

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Base pay, bonus, outstanding retirement programs! The MissionStaffRight Associates has been retained to lead an exclusive search for a Senior ASIC Design Architect to spearhead the development of custom, high-performance silicon for next-gene

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Full-time

180000 - 230000

ASIC & FPGA Design Engineer Senior

Remote or Orlando, Florida

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Today

Job Description You will be the Senior ASIC & FPGA Design Engineer for the ADSWAP CN program. Our team builds the next generation missile and fire control systems that power aerospace and defense grade platforms. We turn ambitious system concepts into hardened hardware, partnering with software, hardware, and systems engineers to deliver integrated, high performance solutions. What You Will Be Doing As the Senior ASIC & FPGA Design Engineer you will lead the end to end creation of sophisticate

Full-time

USD 101,000.00 - 178,135.00 per year

ASIC & FPGA Design Engineer Sr.

Remote or Orlando, Florida

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Today

Job Description You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team supporting the Next Generation Short Range Interceptor (NGSRI). Our team creates the digital heart beats-ASICs and FPGAs-that enable precision engagement aerospace and defense systems for the United States and allied forces. What You Will Be Doing As the Senior ASIC & FPGA Design Engineer you will own the architecture, development, verification, and delivery of the Datalink FPGA that power

Full-time

USD 101,000.00 - 178,135.00 per year

Principal Firmware Engineer - high-speed optical interconnects /custom silicon/ASIC design / microcontroller architectures /

Santa Clara, California

•

Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 154,680.00 - 231,700.00 per year

ASIC & FPGA Design Engineer Sr

Remote or Grand Prairie, Texas

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Today

Job Description You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team within Lockheed Martin Missiles and Fire Control (MFC). Our team creates, prototypes, and fields precision engagement aerospace and defense systems for the U.S. and allied militaries, delivering cutting edge digital solutions that protect the warfighter. What You Will Be Doing As the Senior ASIC & FPGA Design Engineer you will act as a technical leader on one or more defense programs, shap

Full-time

USD 101,000.00 - 178,135.00 per year

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