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San Jose, California

•

Yesterday

We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools. Key Responsibilities: Develop formal verification strategies and methodologiesWrite SystemVerilog Assertions (SVA)Perform property checking, equivalence checking, and CDC/RDC analysisIdentify corner cases missed in simulationCollaborate with RTL teams for design improvements Required Skills: Strong knowledge of formal verification tools (Jasper, VC For

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Full-time

160000 - 170000

Formal Verification Engineer

San Jose, California

•

Yesterday

Job Title: Formal Verification Engineer Location: San Jose, CA Full Time Job Description: We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools. Key Responsibilities: Develop formal verification strategies and methodologies Write System Verilog Assertions (SVA) Perform property checking, equivalence checking, and CDC/RDC analysis Identify corner cases missed in simulation Collaborate with RTL teams for

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Full-time

Senior Staff Engineer, GPU Design Verification (Formal Verification)

San Jose, California

•

Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 198,200.00 - 297,200.00 per year

CPU Processor Power Management Verification Engineer

Santa Clara, California

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Today

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our pr

Full-time

Design Verification Engineer - Ethernet

Santa Clara, California

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29d ago

Design Verification Engineer Overview Upscale AI is developing next-generation Ethernet networking infrastructure optimized for large-scale AI and GPU cluster environments. We are seeking experienced Design Verification Engineers with strong networking and ASIC verification backgrounds to help validate high-performance networking silicon and AI fabric technologies. ResponsibilitiesDevelop and execute verification plans for networking ASICs and SoC designsBuild and maintain SystemVerilog/UVM-base

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Full-time

USD180000 - USD300000 per annum, Benefits: $180k-$300k Annual Salary

Senior Debug Verification Engineer

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 149,100.00 - 215,000.00 per year

ASIC Verification Engineer

Saratoga, California

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Today

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una

Full-time

USD 140,000.00 - 200,000.00 per year

Sr Verification Engineer-Memory Subsystem

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

SoC Verification Engineer - NoC / UVM

San Jose, California

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Today

Full-time

USD 145,600.00 per year

Principal Engineer, GPU Design Verification (Subsystems)

San Jose, California

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Today

Full-time

USD 221,700.00 - 364,800.00 per year

ASIC Verification Engineer

San Jose, California

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Today

Company Description Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world's most critical infrastructure-from data centers to next generation cloud and AI platforms-by secur

Full-time

FPGA Verification Engineer - Avionics

Saratoga, California

•

Today

Full-time

USD 150,000.00 - 250,000.00 per year

Principal Engineer, Design Verification - DDR Memory Subsystems

San Jose, California

•

Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, edge computing, and embedded systems. About the Role

Full-time

USD 209,500.00 - 299,200.00 per year

Sr Software Verification Engineer

Redwood City, California

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Today

At Globus Medical, we move with a sense of urgency to deliver innovations that improve the quality of life of patients with musculoskeletal disorders. Our team is inspired by the needs of these patients, and the surgeons and healthcare providers who treat them. We embrace a culture of exceptional response by partnering with researchers and educators to transform clinical insights into tangible solutions. Our solutions improve the techniques and outcomes of surgery so patients can resume their li

Full-time

Design Verification Engineer at San Jose, CA

San Jose, California

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Today

Position: Senior DV Engineer Location - San Jose, CA, USA FTE/FTC Role Summary The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality. Key Responsibilities Design Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnec

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Full-time

Senior Staff Physical Verification CAD engineer

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 127,630.00 - 191,200.00 per year

Electrical Engineer, Verification & Validation

Mountain View, California

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Today

About us: Aeva's mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices li

Full-time

USD 132,400.00 - 179,200.00 per year

Sr. Staff Engineer (UVM, AMBA, System Verilog & Digital Verification)

San Jose, California

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3d ago

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE:- Sr. Staff Engineer (SystemVerilog & Digital Verification)LOCATION:- SanJose, CA (onsite)This role is part of a large RFC/RFIC/DFT engineering organization, focused on advanced digital verification across complex SoC and mixed-sig

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Contract

$90 - $100

RTL Design Engineer / Design Verification Engineer

Remote

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7d ago

R-069895 RTL Design Engineer Wireless SoC (Remote PST) Location: Remote (must be aligned with PST time zone / willing to work PST hours) We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Required Skills 5+ years of hands-on RTL design experience (

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Full-time, Third Party

Depends on Experience

Design Verification Engineer

Remote

•

8d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

Depends on Experience

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