San Jose, California
•
Yesterday
Role: Lead ASIC DFT Engineer Location: San Jose, CA (Remote, PST time zone preferred) Work Setup: Remote, PST time zone preferred Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) DFT Architecture definition. Must Full chip / Sub system level DFT activities Must Scan & compression (EDT) implementation Must LBIST implementation and verification any BIST exp is Must Coverage improvements (Spyglass work) Must ATPG Good to Have Role Summar
Easy Apply
Full-time, Contract, Third Party
Depends on Experience













