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Santa Clara, California

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Today

Design Verification 1-2 Spots Sunnyvale, CA or Austin TX- Onsite is a must. Main thing is STONG UVM -Networking, ethernet protocols -Python is a plus Here is the JD Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause,

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Contract

70 - 110

SoC Verification Engineer - NoC / UVM

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

Sr. Staff Engineer (UVM, AMBA, System Verilog & Digital Verification)

San Jose, California

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7d ago

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE:- Sr. Staff Engineer (SystemVerilog & Digital Verification)LOCATION:- SanJose, CA (onsite)This role is part of a large RFC/RFIC/DFT engineering organization, focused on advanced digital verification across complex SoC and mixed-sig

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Contract

$90 - $100

Senior Design Verification Engineer

San Jose, California

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13d ago

Immediate need for a talented Senior Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Jose, CA(Onsite). Please review the job description below and contact me ASAP if you are interested. Job ID:26-19462 Pay Range: $150000 - $160000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Key Responsibilities: Design and develo

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Full-time

$150,000 - $160,000

Senior Design Verification Engineer-Need local To CA

Sunnyvale, California

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24d ago

Role: Senior Design Verification Engineer Location -Sunnyvale, CA-Onsite No of Positions - 2 Exp needed - 8 to 10 yrs Duration - Longterm Here is the JD: Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause, and res

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Contract, Third Party

$70 - $80

Staff Engineer, Design Verification

Santa Clara, California

•

Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 113,920.00 - 170,600.00 per year

Senior Staff Engineer, Design Verification

Santa Clara, California

•

Today

Full-time

USD 134,390.00 - 201,300.00 per year

Design Verification Lead Engineer//Fulltime

Sunnyvale, California

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Today

Title :: ASIC Design Verification Lead Engineer Location :: Sunnyvale, CA ( Onsite ) Fulltime Need working experience on C Programming Responsibilities: Work with researchers and architects defining verification plans for each of the different core IP Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest

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Full-time

Principal Engineer, GPU Design Verification (Subsystems)

San Jose, California

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Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 221,700.00 - 364,800.00 per year

Senior Staff Engineer, GPU Design Verification (Formal Verification)

San Jose, California

•

Today

Full-time

USD 198,200.00 - 297,200.00 per year

Principal Engineer, Design Verification - DDR Memory Subsystems

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, edge computing, and embedded systems. About the Role

Full-time

USD 209,500.00 - 299,200.00 per year

Staff Engineer, ASIC Design Verification

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 163,000.00 - 253,000.00 per year

Design Verification Engineer IV

San Jose, California

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Today

Position:Design Verification Engineer IV Job Description:WhatYou\'llBeDoing: Strong SV/UVM expertiseAXI/NOC/Ethernet/PCIe/UCIe Switch expertise is neededCPU ARM/RISC-V with C knowledgeRegression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development.Develop complex self checking test benches with constra

Full-time

SoC Design Verification Engineer

San Jose, California

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Today

We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute SoC-level validation and performance verification strategyBuild system-level testbenches, workloads, and performance modelsAnalyze performance bottlenecks acros

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Full-time

160000 - 175000

Staff/Principal Engineer - Design Verification (SoC expert/lead)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: ASIC Design Verification SoC Lead (Technical lead role) Position Description: This is a position for lead member in Micron's ASIC Verification and Emulation group.

Full-time

USD 168,000.00 - 336,000.00 per year

Hardware Design Verification/Test Engineer

San Jose, California

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20d ago

Position: Hardware Design Verification/Test Engineer Location: San Jose, CA - Onsite Roles & Responsibilities: Participate on a project team of engineers involved in hardware development and testing.Define system-level Design Verification Test procedures.Perform complex system-level unit and integration testing.Debug and mitigate complex system-level issues.Collaborate with hardware design, software/diagnostic, and manufacturing test engineers to develop and execute product test strategies.Deve

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Contract

Depends on Experience

Design Verification Engineer at San Jose, CA

San Jose, California

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Today

Position: Senior DV Engineer Location - San Jose, CA, USA FTE/FTC Role Summary The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality. Key Responsibilities Design Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnec

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Full-time

Staff/Principal Engineer. ASIC Design Verification (DDR expert)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff/Principal ASIC SoC Design Verification Engineer - DDR expert (Technical role) Position Description: This is a position for Staff technical member of Micron's

Full-time

USD 168,000.00 - 336,000.00 per year

Design Verification Engineer

Remote

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12d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

Depends on Experience

RTL Design Engineer / Design Verification Engineer

Remote

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11d ago

R-069895 RTL Design Engineer Wireless SoC (Remote PST) Location: Remote (must be aligned with PST time zone / willing to work PST hours) We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Required Skills 5+ years of hands-on RTL design experience (

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Full-time, Third Party

Depends on Experience

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