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Santa Clara, California

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Yesterday

Roles & Responsibilities: We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools. Key Responsibilities: Develop formal verification strategies and methodologies Write SystemVerilog Assertions (SVA) Perform property checking, equivalence checking, and CDC/RDC analysis Identify corner cases missed in simulation Collaborate with RTL teams for design improvements Required Skills: Strong knowledge of fo

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Contract, Third Party

Depends on Experience

Senior Staff Engineer, GPU Design Verification (Formal Verification)

San Jose, California

•

Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 198,200.00 - 297,200.00 per year

Formal DV Engineer

Santa Clara, California

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2d ago

We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools. Key Responsibilities: Develop formal verification strategies and methodologies Write SystemVerilog Assertions (SVA) Perform property checking, equivalence checking, and CDC/RDC analysis Identify corner cases missed in simulation Collaborate with RTL teams for design improvements Required Skills: Strong knowledge of formal verification tools (Ja

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Part-time

Depends on Experience

Design Verification Engineer

Remote or Hybrid in Sunnyvale, California

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4d ago

Title DesignVerificationEngineer-Performance Modelling Location Sunnyvale CA, Austin TX or Remote Key ResponsibilitiesDevelop, maintain, and enhance STL (Scenario/Test List) generation scripts andperformancevalidation infrastructure.Monitorperformanceregression status and track keyperformanceindicators (KPIs) across IP and subsystem levelverificationenvironments.Analyze regression failures and collaborate with IP, Design, andDVowners to drive issue resolution.Debugverificationtests that fail t

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Full-time

150,000 - 170,000

Senior Design Verification Engineer

San Jose, California

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18d ago

Immediate need for a talented Senior Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Jose, CA(Onsite). Please review the job description below and contact me ASAP if you are interested. Job ID:26-19462 Pay Range: $150000 - $160000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Key Responsibilities: Design and develo

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Full-time

$150,000 - $160,000

Staff Engineer, Design Verification

Santa Clara, California

•

Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 113,920.00 - 170,600.00 per year

Design Verification Engineer at San Jose, CA

San Jose, California

•

Today

Position: Senior DV Engineer Location - San Jose, CA, USA FTE/FTC Role Summary The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality. Key Responsibilities Design Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnec

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Full-time

Senior Staff Engineer, Design Verification

Santa Clara, California

•

Today

Full-time

USD 134,390.00 - 201,300.00 per year

Hardware Design Verification/Test Engineer

San Jose, California

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25d ago

Position: Hardware Design Verification/Test Engineer Location: San Jose, CA - Onsite Roles & Responsibilities: Participate on a project team of engineers involved in hardware development and testing.Define system-level Design Verification Test procedures.Perform complex system-level unit and integration testing.Debug and mitigate complex system-level issues.Collaborate with hardware design, software/diagnostic, and manufacturing test engineers to develop and execute product test strategies.Deve

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Contract

Depends on Experience

Verification Engineer - Aeromechanical (Design & Test)

Palo Alto, California

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Today

Pivotal is the leader in the emerging market of electric Vertical Takeoff and Landing (eVTOL) aircraft. We design, develop, and manufacture light eVTOL aircraft and are renowned for the BlackFly aircraft the world's first light eVTOL to fly manned missions and enter the consumer market. Efficient, compact, and simple, Pivotal aircraft are designed for a wide range of consumer, public service, and defense applications. Our distinctive tilt-aircraft architecture and scalable platform have been fly

Full-time

USD 115,000.00 - 145,000.00 per year

Senior Design Verification Engineer-Need local To CA

Sunnyvale, California

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29d ago

Role: Senior Design Verification Engineer Location -Sunnyvale, CA-Onsite No of Positions - 2 Exp needed - 8 to 10 yrs Duration - Longterm Here is the JD: Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause, and res

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Contract, Third Party

$70 - $80

Principal Design Verification Engineer | Full-Time/Permanent Role

Santa Clara, California

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2d ago

Role: Principal Design Verification Engineer Location: Santa Clara, CA (Onsite) Job Type: Full-Time / Permanent Job SummaryWe are seeking an experienced Principal Design Verification Engineer to lead verification efforts for complex, high-performance SoC and networking ASIC designs. This is a hands-on technical leadership role responsible for architecting advanced verification environments, developing comprehensive verification strategies, and driving successful silicon tape-outs for next-gener

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Full-time

Depends on Experience

Staff Engineer, ASIC Design Verification

San Jose, California

•

Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 163,000.00 - 253,000.00 per year

Design Verification Engineer

Remote

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2d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

Depends on Experience

Staff/Principal Engineer. ASIC Design Verification (DDR expert)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff/Principal ASIC SoC Design Verification Engineer - DDR expert (Technical role) Position Description: This is a position for Staff technical member of Micron's

Full-time

USD 168,000.00 - 336,000.00 per year

Staff/Principal Engineer - Design Verification (SoC expert/lead)

San Jose, California

•

Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: ASIC Design Verification SoC Lead (Technical lead role) Position Description: This is a position for lead member in Micron's ASIC Verification and Emulation group.

Full-time

USD 168,000.00 - 336,000.00 per year

RTL Design Engineer / Design Verification Engineer

Remote

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16d ago

R-069895 RTL Design Engineer Wireless SoC (Remote PST) Location: Remote (must be aligned with PST time zone / willing to work PST hours) We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Required Skills 5+ years of hands-on RTL design experience (

Easy Apply

Full-time, Third Party

Depends on Experience

Design Verification Engineer (eInfochips Inc)

San Jose, California

•

Today

Position:Design Verification Engineer (eInfochips Inc) Job Description:WhatYou\'llBeDoing: Strong SV/UVM expertiseAXI/NOC/Ethernet/PCIe/UCIe Switch expertise is neededCPU ARM/RISC-V with C knowledgeRegression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development.Develop complex self checking test benche

Full-time

Staff DV Engineer

Saratoga, California

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Today

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una

Full-time

USD 120,000.00 - 220,000.00 per year

Principal DV Engineer

Saratoga, California

•

Today

Full-time

USD 120,000.00 - 220,000.00 per year

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