Santa Clara, California
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Yesterday
Sr. Layout Design Engineer with SRAM Experience Location : Santa Clara, CA Location : Remote 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout. Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions. Solid grasp of SRAM and memory layout principles. Extensive experience in Cadence Virtuoso applied to custom layout cr
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Full-time, Third Party
Depends on Experience













