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Sunnyvale, California

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Today

Hi, Tittle- Physical Design Lead Engineer Location :: Sunnyvale, CA onsite Job Type- Fulltime Must have- Fusion compiler tool knowledge is a requirement for this job. JD- What are the top non-negotiable skill sets required for this role? Strong understanding in the RTL2GDSII flow and design tapeouts in 5nm, 3nm, 2nm process technologies Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge. Experience working with most EDA tools like Fusion

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Full-time

Physical Design Engineer

Mountain View, California

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8d ago

Physical Design Engineer (PD / PnR / PPA / Timing Closure) Location: Mountain View CA (Onsite) Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floor planning, power planning, placement, clock tree synthesis (CTS), routing, and physical veri

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Contract

Depends on Experience

Physical Design Engineer 69105

Mountain View, California

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Today

Physical Design Engineer Seeking a Physical Design Engineer in Mountain View, CA (Onsite) with strong expertise in Place & Route (PnR), timing closure, STA, and PPA optimization for advanced semiconductor designs. Key skills include floorplanning, placement, CTS, routing, EMIR analysis, SDC constraints, signoff methodologies, and experience with EDA tools like Fusion Compiler, ICC2, PrimeTime, and Innovus. Location: Mountain View, CA For Immediate Consideration: Suryansh PRIMUS Global Servi

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Full-time

$145000 - 150000

ASIC Physical Design Engineer

San Jose, California

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2d ago

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Great base pay, bonus, terrific benefits and exceptional 401k! he MissionStaffRight Associates is recruiting to identify a high-caliber ASICPhysical Design Engineer to spearhead the structural realization of next-generation System-on-Chip (So

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Full-time

170000 - 220000

Physical Design Engineer

Mountain View, California

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10d ago

Only Local independent candidates are allowed to apply for this Role. Location: Mountainview, CA Core Technical SkillsASIC Implementation: Full RTL-to-GDSII flow, Block-level Place & Route (PnR), Floorplanning, Power Planning, Placement, and Routing. Timing & Signoff: Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Timing Constraints (SDC), and Timing Closure (Setup/Hold/Transition/Noise). Design Optimization: Power-Performance-Area (PPA) optimization, low-power design techniques, and

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Full-time, Third Party

Depends on Experience

Physical Design Engineer

San Jose, California

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23d ago

Position: Physical Design Engineer / Staff Engineer Location:San Jose CA Contract More than 12 months Relocation consultants are also considerable.. Job Responsibilities: We are seeking experienced Physical Design Engineers with expertise in top-level signoff for complex SoCs on advanced nodes (7nm/5nm/3nm). Candidates should have multiple full-cycle tapeouts and strong experience in signoff-to-tapeout closure. Key Responsibilities: Drive full-chip/top-level signoff activities Collaborate with

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Contract

Depends on Experience

Physical Design Engineer (PnR / PPA / Timing Closure) (Only W2))

Mountain View, California

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2d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure

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Full-time

140,000 - 150,000

Electrical / Analog Design Engineer

Milpitas, California

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3d ago

Maxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a Electrical / Analog Design Engineer. Job Description: Job Title: Electrical / Analog Design Engineer Job Type: Contract Job Location: Milpitas, CA Work Schedule: On-site Pay Rate: $60, Based on experience Description: We are seeking an experienced Senior Electrical Engineer to lead the design, development, and validation of complex electrical systems and hardware produc

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Contract

Depends on Experience

Mechanical Design Engineer

Santa Clara, California

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Yesterday

Mechanical Design Engineer Location Santa Clara, CA ((Onsite 5 days/week) Contract Mandatory Areas Must Have Skills Skill 1 Mechanical Design Engineer with experience in hardware/mechanism design and development of vacuum systems, vacuum chambers, vacuum isolation technologies, and support equipment Skill 2 Preferred experience in the semiconductor manufacturing capital equipment space with knowledge of semiconductor Skill 3 Work with OEM suppliers to specify, develop, & document components re

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Contract

Depends on Experience

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Sunnyvale, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

Full-time

USD 175,000.00 - 280,000.00 per year

Design Engineer 4

Newark, California

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24d ago

Job Title: Engineering & IT - Design Engineer 4 Start/End Dates: 25/05/2026 - 31/12/2026 Candidate Location Requirements: Newark, California, Engineer, Exterior Trim We are currently seeking an Exterior Trim Engineer. This position requires a responsibility for designing and developing parts of the exterior systems of a world class vehicle in terms of both styling and function. Our ideal candidate exhibits a can-do attitude and approaches his or her work with vigor and determination. Candidates

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Third Party, Contract

Depends on Experience

Design Verification Engineer - Ethernet

Santa Clara, California

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28d ago

Design Verification Engineer Overview Upscale AI is developing next-generation Ethernet networking infrastructure optimized for large-scale AI and GPU cluster environments. We are seeking experienced Design Verification Engineers with strong networking and ASIC verification backgrounds to help validate high-performance networking silicon and AI fabric technologies. ResponsibilitiesDevelop and execute verification plans for networking ASICs and SoC designsBuild and maintain SystemVerilog/UVM-base

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Full-time

USD180000 - USD300000 per annum, Benefits: $180k-$300k Annual Salary

Design Verification Lead Engineer//Fulltime

Sunnyvale, California

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Today

Title :: ASIC Design Verification Lead Engineer Location :: Sunnyvale, CA ( Onsite ) Fulltime Need working experience on C Programming Responsibilities: Work with researchers and architects defining verification plans for each of the different core IP Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest

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Full-time

Product Design Engineer V || Cupertino, CA (Onsite)

Cupertino, California

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9d ago

Our client, a leading global consumer electronics and technology company, is looking to hire a Contract Product Design FEA Engineer in Cupertino, CA. Pay Rate Range:$90 to $110/hr on w2, depending on experience Responsibilities: We are seeking a Contract Product Design FEA Engineer to play a critical role in predictive engineering and product development. In this position, you will leverage your expertise in mechanics, materials, and numerical simulation methods to support the structural desig

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Third Party, Contract

$111.94 - $111.94

Staff/Principal Engineer - Design Verification (SoC expert/lead)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: ASIC Design Verification SoC Lead (Technical lead role) Position Description: This is a position for lead member in Micron's ASIC Verification and Emulation group.

Full-time

USD 168,000.00 - 336,000.00 per year

Lead Mechanical/ Product Design Engineer, Special Projects

Remote or San Francisco, California

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Today

Join the Sleep Fitness Movement At Eight Sleep, we're on a mission to fuel human potential through optimal sleep. As the world's first sleep fitness company, we're redefining what it means to be well-rested and building the most advanced hardware, software, and AI technology to make it possible. Our products power peak mental, physical, and emotional performance by transforming every night of sleep into a personalized, data-driven recovery experience. We are trusted by high performers, professi

Full-time

USD 140,000.00 - 225,000.00 per year

Product Design Engineer (III)

Mountain View, California

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Today

Position: Product Design Engineer () Location: Mountain View, CA -Hybrid Duration: 06+ months Contract Job ID: 177656 Pay Range: $95 - $105/hour on W2 Description: As a Product Design Engineer, you are considered a go-to expert in one area within Product Design, demonstrating engineering expertise through user- or consumer-focused product influence in multiple cross-functional areas. You participate in a greater team initiative (e.g., publishing technical documents, creating/improving proces

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Full-time

Compensation information provided in the description

Senior Engineer, Analog Design Engineering

San Jose, California

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Today

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI

Full-time

USD 159,890.00 - 192,050.00 per year

Senior Engineer, GPU RTL Design - Pixel Pipe

San Jose, California

•

Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 139,000.00 - 208,400.00 per year

Senior Engineer, Digital Design Engineering

San Jose, California

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Today

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's inno

Full-time

USD 156,853.00 - 201,756.00 per year

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