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Today
Title: Verification Engineer Location: Remote, Duration: 12 months 1. Strong System Verilog & UVM experience 2. Digital design/RTL verification expertise 3. Experience with verification methodologies/tools (formal verification, coverage, simulation, scripting) 4. Familiarity with AXI protocol 5. Familiarity with UCIe would be a nice-to-have
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Depends on Experience




