Upf jobs in california

Remote

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4d ago

Required: Understanding of real-time payments, ACH, RTGS, SEPA, SWIFT Familiarity with ISO 20022 messaging standards Knowledge of the CI-HUB architecture and product (installation, configuration, operation) Knowledge of UPF (installation, configuration, operation) Knowledge of the CI-HUB product lifecycle. Cloud & DevOps: Experience with cloud-native platforms (AWS, Azure, Google Cloud Platform) Microservices architecture and containerization (Docker, Kubernetes) Integration & APIs: RESTful API

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Contract

60 - 65

Design Engineer

Sunnyvale, California

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9d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

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Third Party, Contract

$82 - $85

PD Engineer

Sunnyvale, California

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Today

Senior Physical Design Engineer Sunnyvale, CA, USA Fulltime Visa- G C and U S C Only We are looking for a Senior Physical Design Engineer with 814 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA. What You will Do: Drive physical design flow: synthesis, floorplanning, placement, CTS, rout

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Full-time

Depends on Experience

Staff Physical Design Engineer

Sunnyvale, California

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6d ago

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field8 12 years of experience in ASIC physical designProven experience in full-chip or large block implementation and tapeoutsStrong expertise in:Floorplanning and power planningPlacement, CTS, routing, and physical verificationStatic Timing Analysis (STA) and timing closureHands-on experience with industry-standard tools such as: Synopsys ICC2 / Cadence InnovusSynopsys PrimeTimeMentor CalibreExperience with

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Contract, Third Party

Depends on Experience

Design Verification Engineer

San Jose, California

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4d ago

Position: Design Verification Engineer Type/Duration: Full time//Permanent Location: San Jose, CA (5 Days onsite in a week) Summary: We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments. Key Responsibilities: Develop and maintain UVM-based verification environments Create test plans, testcases, and coverage models Perform functional verification of RTL designs Debug RTL and testbench issues Driv

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Full-time, Third Party

Depends on Experience

Design Verification Engineer

Remote

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5d ago

Hi - Full Time Role Job Title: Design Verification Engineer -Performance Modelling Location : Remote USA Strong understanding of SV and UVM and good debugging skills.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely wi

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Full-time

Depends on Experience

DFx Verification Engineer

Santa Clara, California

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Today

DFx Verification Engineer Location: - Santa Clara, CA (Onsite) Exp Range: - 5-20 Years of experience Long Term Contract (12 Months +) / Full Time Position JD Key Responsibilities Develop and execute verification plans for DFx features including: Scan (stuck-at, transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Create and maintain testbenches using SystemVerilog/UVM for DFx validation Verify: Scan chain integrity and connectivity T

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Full-time, Part-time, Contract, Third Party

Physical Design Engineer & DV Engineers

Sunnyvale, California

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20d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Design Engineer III

Sunnyvale, California

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Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

Design Verification Engineer

San Diego, California

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19d ago

Design Verification EngineerLocation: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job SummaryWe are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC verification to join our semiconductor team. The ideal candidate will have extensive experience in SystemVerilog, UVM, and protocol verification, with a proven track record of developing robust verification environments and achieving coverage closure. Key ResponsibilitiesDevelop and execute comprehensive ve

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Full-time, Third Party

180,000 - 200,000

Emulation Verification Engineer

San Francisco, California

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Today

Imagine what you could at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengt

Full-time

Lead Functional Product Engineer, Power Analysis

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments. Key Responsibilities Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages Reproduce, debug, and resolve customer-reported issues in power an

Full-time

USD 114,800.00 - 213,200.00 per year

Digital Verification Engineer

South San Francisco, California

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Today

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Job Description & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team. This position offers

Full-time

USD 131,000.00 - 243,000.00 per year

Principal CAD Engineer

Santa Clara, California

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Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd

Full-time

USD 195,000.00 - 292,000.00 per year

AI/ML Driven ASIC Design and Implementation Automation Engineer

San Diego, California

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Today

As an AI/ML driven ASIC Design and Implementation Automation Engineer in our Advanced Chip Engineering (ACE) organization, you will work in a dynamic environment to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and quality) for SoC and IP development teams across the organization. You'll be working and connecting with AI/ML and automation experts in the industry as well as academia to explore state-of-the-art AI/ML CAD techniques as

Full-time

USD 147,900.00 - 203,400.00 per year

Staff Semiconductor Power Engineer (ICB4)

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Role Overview: We are seeking a highly skilled and motivated Staff Power Engineer to join our semiconductor design team. In this role, you will be the primary driver for our power strategies, taking full ownership of end-to-end power definition, analy

Full-time

USD 121,900.00 - 195,000.00 per year

FPGA Engineer Engineer (eInfochips)

San Jose, California

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Today

Position: FPGA Engineer Engineer (eInfochips) Job Description: Job Description Location: San Jose CA and Austin TX (Day-1 Onsite) Experience: 9+ Years What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs.Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)Experience with high speed PCIe designs and protocols.Experience with Industry standard interface protocols such as AXI, APB, etc.Experience

Full-time

Low Power Design/Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Job Overview: Design adaptive power management controller, on-chip sensor controller and digital power meter.Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.Work closely with technology/circuit design team to close IP block specification/requirement.Work cl

Full-time

USD 115,600.00 - 173,400.00 per year

Hardware Design Engineer - Graphics Silicon Implementation

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: Qualcomm CDMA Technologies, is the world leader in wireless ICs powering the majority of 3G & 4G devices and the largest fabless semiconductor company in the world. The Graphics team is looking for an Engineer to work on QUALCOMMs Adreno Graphics cores in the area of implementation and methodology. The successful candidate will work in Adreno GPU team and will be respon

Full-time

USD 161,800.00 - 242,600.00 per year

Principal DFT Engineer (Silicon Engineering)

Irvine, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 210,000.00 - 340,000.00 per year

Upf jobs in California, USA