Upf jobs in sunnyvale, ca

Remote

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4d ago

Required: Understanding of real-time payments, ACH, RTGS, SEPA, SWIFT Familiarity with ISO 20022 messaging standards Knowledge of the CI-HUB architecture and product (installation, configuration, operation) Knowledge of UPF (installation, configuration, operation) Knowledge of the CI-HUB product lifecycle. Cloud & DevOps: Experience with cloud-native platforms (AWS, Azure, Google Cloud Platform) Microservices architecture and containerization (Docker, Kubernetes) Integration & APIs: RESTful API

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Contract

60 - 65

Design Engineer

Sunnyvale, California

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9d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

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Third Party, Contract

$82 - $85

PD Engineer

Sunnyvale, California

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2d ago

Senior Physical Design Engineer Sunnyvale, CA, USA Fulltime Visa- G C and U S C Only We are looking for a Senior Physical Design Engineer with 814 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA. What You will Do: Drive physical design flow: synthesis, floorplanning, placement, CTS, rout

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Full-time

Depends on Experience

Staff Physical Design Engineer

Sunnyvale, California

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5d ago

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field8 12 years of experience in ASIC physical designProven experience in full-chip or large block implementation and tapeoutsStrong expertise in:Floorplanning and power planningPlacement, CTS, routing, and physical verificationStatic Timing Analysis (STA) and timing closureHands-on experience with industry-standard tools such as: Synopsys ICC2 / Cadence InnovusSynopsys PrimeTimeMentor CalibreExperience with

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Contract, Third Party

Depends on Experience

Design Verification Engineer

San Jose, California

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4d ago

Position: Design Verification Engineer Type/Duration: Full time//Permanent Location: San Jose, CA (5 Days onsite in a week) Summary: We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments. Key Responsibilities: Develop and maintain UVM-based verification environments Create test plans, testcases, and coverage models Perform functional verification of RTL designs Debug RTL and testbench issues Driv

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Full-time, Third Party

Depends on Experience

DFx Verification Engineer

Santa Clara, California

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3d ago

DFx Verification Engineer Location: - Santa Clara, CA (Onsite) Exp Range: - 5-20 Years of experience Long Term Contract (12 Months +) / Full Time Position JD Key Responsibilities Develop and execute verification plans for DFx features including: Scan (stuck-at, transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Create and maintain testbenches using SystemVerilog/UVM for DFx validation Verify: Scan chain integrity and connectivity T

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Full-time, Part-time, Contract, Third Party

Physical Design Engineer & DV Engineers

Sunnyvale, California

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20d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Design Engineer III

Sunnyvale, California

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Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

Lead Functional Product Engineer, Power Analysis

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments. Key Responsibilities Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages Reproduce, debug, and resolve customer-reported issues in power an

Full-time

USD 114,800.00 - 213,200.00 per year

Principal CAD Engineer

Santa Clara, California

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Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd

Full-time

USD 195,000.00 - 292,000.00 per year

FPGA Engineer Engineer (eInfochips)

San Jose, California

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Today

Position: FPGA Engineer Engineer (eInfochips) Job Description: Job Description Location: San Jose CA and Austin TX (Day-1 Onsite) Experience: 9+ Years What candidate will Be Doing: Proficient in Verilog/System Verilog coding constructs.Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)Experience with high speed PCIe designs and protocols.Experience with Industry standard interface protocols such as AXI, APB, etc.Experience

Full-time

Staff Semiconductor Power Engineer (ICB4)

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Role Overview: We are seeking a highly skilled and motivated Staff Power Engineer to join our semiconductor design team. In this role, you will be the primary driver for our power strategies, taking full ownership of end-to-end power definition, analy

Full-time

USD 121,900.00 - 195,000.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

Distinguished CAD Engineer

Santa Clara, California

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Today

Full-time

USD 279,500.00 - 419,500.00 per year

Principal DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 220,000.00 - 355,000.00 per year

Digital Verification Engineer

South San Francisco, California

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Today

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Job Description & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team. This position offers

Full-time

USD 131,000.00 - 243,000.00 per year

Core Engineering - Design Engineer III

Sunnyvale, California

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Today

Job#: 3045115 Job Description: Core Engineering - Design Engineer Location: Sunnyvale, California (Partial Remote) 3 days / week onsite Compensation: $70- $80 Hourly Role Overview This position is for a Design Verification engineer focused on wearables silicon accelerator IPs. The role involves testbench development, coverage-driven verification, RTL debug, and power and performance measurement. The successful candidate will work with a small team to build and run testbenches, analyze cove

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Full-time

$70 - $80 per hour

STA Engineer

Santa Clara, California

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Today

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-syste

Full-time

USD 153,200.00 - 229,800.00 per year

Senior Staff Engineer, GPU Design Verification (Formal Verification)

San Jose, California

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Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 198,200.00 - 297,200.00 per year

IP Release Principal Engineer

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 158,600.00 - 237,600.00 per year

Upf jobs in Sunnyvale, CA, USA