Uvm jobs in california

Sunnyvale, California

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5d ago

Hello, Hope you are doing well. Title: ARM IP Verification Engineer Location: Sunnyvale, CA Are you passionate about building robust verification environments for next-gen silicon? We are looking for an experienced ARM IP-Level Verification Engineer to join our team in Sunnyvale, CA. If you thrive on architecting complex UVM testbenches, driving coverage closure, and developing custom VIP from the ground up, we want to hear from you. Key Focus Areas: SystemVerilog & UVM mastery Custom VIP de

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Contract

50 - 60

SoC Verification Engineer - NoC / UVM

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

Senior Emulation/Verification Engineer In Bay Area, CA || Hybrid Role

Hybrid in Menlo Park, California

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Today

Role: Senior Emulation/Verification EngineerDuration: Long TermLocation: Bay Area, CA || Hybrid Role Job Description-: We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

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Contract

Depends on Experience

Design Verification Engineer

San Jose, California

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Today

Hi, Role : Design Verification Engineer Location: San Jose, CA - Onsite Hands-on experience with industry-standard verification methodologies like System Verilog/UVM and understand how to build scalable, reusable testbenches. Experience handling vendors and integration of IP/VIP sUVM/System Verilog Thanks and Regards, Praveenkumar

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Third Party, Contract

Depends on Experience

SoC Design Verification Engineer

San Jose, California

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4d ago

Position Title: SoC Design Verification Engineer Location: San Jose, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute S

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Full-time, Third Party

Depends on Experience

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

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Today

Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ Years Job Type: Contract / Long-Term Job Summary We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP. The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure,

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Full-time, Part-time, Contract, Third Party

Design Verification Engineer

San Jose, California

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19d ago

Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required 8+ years of Design Verification experience in s

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Contract

Depends on Experience

Verification Lead – Memory Controller (CHI-G / DFI)

San Jose, California

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Today

Role : Verification Lead Memory Controller (CHI-G / DFI) Location : San Jose, CA (Onsite) | Lead Level | Exp : 10+ Years We are looking for a Verification Lead with strong hands-on experience in Memory Controller Design Verification. Key Skills: 10+ years Design Verification experience 3+ years in Verification Lead/Management DDR4/DDR5/LPDDR Memory Controller verification ARM CHI / CHI-G protocol verification DFI interface & PHY verification Expert SystemVerilog / UVM AXI4 / ACE / AHB /

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Contract

Depends on Experience

Design Engineer

Sunnyvale, California

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10d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

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Third Party, Contract

$82 - $85

ASIC Emulation Engineer

San Jose, California

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20d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

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Contract

60 - 75

Design Verification Engineer (Only W2)

Santa Clara, California

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Today

Job descriptionYour Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers'' specifications whether they''re a major telecom organization or automotive company, etc. What You Can Expect As a leading member of the Network S

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Full-time

150,000 - 300000

Senior Emulation Engineer

San Jose, California

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Today

We have an open Emulation Engineer position in San Jose, USA. Senior Emulation Engineer Location: San Jose, CA Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software br

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Third Party, Contract

Depends on Experience

ASIC/FPGA Verification Engineer 5

El Segundo, California

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Today

This posting is for a contract assignment and is not a full-time employment offer with Boeing. Candidates selected for roles will be employed as contract workers through a Boeing approved 3rd party for the duration of the specified project. Regular and predictable attendance is required Work statement is a non-managerial role, non-leadership role. Resolves complex issues on critical programs related to architectural approaches, requirements, specifications and design. Leads technical aspect of p

Full-time

Design Verification Engineer

Remote

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6d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

Depends on Experience

Design Engineer III

Sunnyvale, California

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Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

Emulation Verification Engineer

San Francisco, California

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Today

Imagine what you could at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengt

Full-time

ASIC Verification Engineer

Irvine, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: ASIC Verification Engineer High Speed Interconnect Product (HSIP) Group Broadcom is a global leader and innovator in semiconductor solutions for wired and wireless communications. The High Speed Interconnect Product (HSIP) line of business produces th

Full-time

USD 101,000.00 - 162,000.00 per year

Digital Engineer (FPGA/ ASIC)

Los Angeles, California

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Today

Location: Los Angeles, CA Salary: $70.00 USD Hourly - $95.00 USD Hourly Description: Job Title: Digital Engineer (FPGA/ ASIC) Duration: 1+ year (Possible extension or Perm) Location: About the Role We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Using Model-based Engineering, DevSecOps and Agil

Contract

Compensation information provided in the description

C - Focused Design Verification Engineer

San Diego, California

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Today

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integratio

Full-time

Design Verification Engineer

San Diego, California

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20d ago

Design Verification EngineerLocation: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job SummaryWe are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC verification to join our semiconductor team. The ideal candidate will have extensive experience in SystemVerilog, UVM, and protocol verification, with a proven track record of developing robust verification environments and achieving coverage closure. Key ResponsibilitiesDevelop and execute comprehensive ve

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Full-time, Third Party

180,000 - 200,000

Uvm jobs in California, USA