Santa Clara, California
•
20d ago
No Contract Only Fulltime Title: Design Verification Engineer Loc: Santa Clara CA(Weekly 5 days onsite) Type: Fulltime Key Responsibilities: DV Engineer with strong expertise in SystemVerilog, UVM, and AMBA protocols. Experienced in building IP/SoC testbenches, writing test plans from design specs, and closing functional/code coverage. Skilled in power-aware (UPF/CPF) simulations, debugging RTL failures, and collaborating across DFT, PD, and post-silicon teams to ensure high-quality design de
Easy Apply
Full-time
Depends on Experience










