verilog Jobs

281 - 300 of 359 Jobs

Embedded Software EngineerJob Title - Embedded Software Engineer

Aduril IndustriesCompany Name - Aduril Industries

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Costa Mesa, California, USA

Full-time

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and c

Embedded Software Engineer, Electronic WarfareJob Title - Embedded Software Engineer, Electronic Warfare

Aduril IndustriesCompany Name - Aduril Industries

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Costa Mesa, California, USA

Full-time

Embedded Haskell DeveloperJob Title - Embedded Haskell Developer

Aduril IndustriesCompany Name - Aduril Industries

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Costa Mesa, California, USA

Full-time

ASIC Design LeaderJob Title - ASIC Design Leader

Kratos Defense and Security Solutions, Inc.Company Name - Kratos Defense and Security Solutions, Inc.

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Crane, Indiana, USA

Full-time

Job Description Permanent Residents and Visa-holders are not eligible for employment. General Summary This full-time position is in the Systems Development Department of Kratos SRE and is a highly motivated and self-driven role that will focus on leading development efforts for next-generation technologies for microelectronics Key Responsibilities Provide technical leadership in the development and evaluation of custom integrated circuit designs for defense applications,Investigate, research

FPGA Consultant ( FPGA , RTL ,Highspeed transceivers , 25G , PAM4 , PON Network , Python)Job Title - FPGA Consultant ( FPGA , RTL ,Highspeed transceivers , 25G , PAM4 , PON Network , Python)

Wise Equation Solutions Inc.Company Name - Wise Equation Solutions Inc.

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San Jose, California, USA

Full-time

FPGA Consultant San Jose, CA ( Onsite) Full time permanent Hire F2F Interview at client site 12+ years of hardware engineering and architecture with experience delivering mission critical products. 10+ year's experience with FPGA development. RTL (Verilog / VHDL) Proficiency Experience with high-speed transceivers at 25G and above including PAM-4 modulation, transmission line theory, trans-impedance amplifiers, Understanding of point-to-multipoint PON networks Comfortable with scripting language

Static Timing Analysis? EngineerJob Title - Static Timing Analysis? Engineer

ApolisCompany Name - Apolis

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San Jose, California, USA

Full-time, Contract

Job Title: Static Timing Analysis Engineer Location: San Jose ,CA (Onsite) Contract: 12+ MonthsWhat candidate will Be Doing: Technical Requirement: Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes ba

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Contract, Third Party

What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.Option to engage in block-level RTL design or block or top-level IP integration.Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the S

Mixed-Signal Design Verification EngineerJob Title - Mixed-Signal Design Verification Engineer

Talent Junction, LLC.Company Name - Talent Junction, LLC.

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San Jose, California, USA

Contract, Third Party

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

RTL EngineerJob Title - RTL Engineer

CloudiousCompany Name - Cloudious

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Santa Clara, California, USA

Contract

Title: RTL Engineer Location: Santa Clara, CA (Day-1 onsite) Duration: 6 Months Role: Integrate RISC-V Core to SoC Key Responsibilities Integrate RISC-V CPU cores into SoC designs, collaborating with cross-functional teams (DV, physical design, architecture, verification, and post-silicon validation) to ensure seamless delivery. Develop and optimize RTL (using Verilog/SystemVerilog) for core, interconnect, and memory subsystems. Evaluate and integrate third-party IP, ensuring performance, power,

RTL Engineer: Integrate RISC-V Core to SoCJob Title - RTL Engineer: Integrate RISC-V Core to SoC

Intelliswift Software IncCompany Name - Intelliswift Software Inc

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Santa Clara, California, USA

Contract

Job Title: RTL Engineer: Integrate RISC-V Core to SoC Location(s): Santa Clara, CA - Onsite Must Have skills: 5+ years of experience in RTL design, SoC integration, or related areas.Strong hands-on experience with hardware description languages (Verilog, SystemVerilog, VHDL), EDA tools, and simulators (VCS, NC, Verilator).Deep understanding of SoC design, integration, and high-performance interfaces (e.g., AXI, TileLink, PCIe, Ethernet).Proven ability to debug and optimize designs for functiona

STA EngineerJob Title - STA Engineer

Kutir IncCompany Name - Kutir Inc

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San Jose, California, USA

Contract, Third Party

Position: STA Engineer Location: Onsite San Jose CA Duration: 6+ months In Person Interview is must Job Description: Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or t

STA EngineerJob Title - STA Engineer

Cybotic Systems LLCCompany Name - Cybotic Systems LLC

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San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develop efficient methodolog

SDC EngineerJob Title - SDC Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Third Party, Contract

Must have/Primary skills: Full chip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees full chip SDCs and works with physical design and DFT teams to close full chip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develops efficient methodology to promote block level SDCs to full chip, and to bring f

Design Verification Engineer (GPU)Job Title - Design Verification Engineer (GPU)

BayOne SolutionsCompany Name - BayOne Solutions

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San Jose, California, USA

Contract

Job Title - Design Verification Engineer (GPU) Duration 9 + Month (With the possibility of extension) Location:- San Jose (Onsite) Pay Rate :- $100/hr. - 120/hr. on w2 Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including th

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Contract, Third Party

Position: Senior ASIC Design Engineer Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Colla

Senior Design Verification EngineerJob Title - Senior Design Verification Engineer

PeopleNTechCompany Name - PeopleNTech

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Mountain View, California, USA

Contract, Third Party

Position: Senior Design Verification Engineer Location: Mountainview, California Experience: 7 to 12 years What candidate will Be Doing: Strong expertise along-with complex SoC/IP debug is mustAt-least 5+ years of experience in System Verilog HVL and C/C++.AMBA AXI bus along-with ARM or C based processorBi-frost/Processor based C and SV/UVM mix Verification. What we are looking for: A bachelor s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in

Principal Verification EngineerJob Title - Principal Verification Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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Raleigh, North Carolina, USA

Full-time

A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to help develop cutting-edge technologies that accelerate and secure data. In this full-time role, the Principal Verification Engineer will report to the Director of Design Engineering and take a key role in product development a

Principal Verification EngineerJob Title - Principal Verification Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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San Jose, California, USA

Full-time

Silicon Verification Engineer 2Job Title - Silicon Verification Engineer 2

Dexian DISYSCompany Name - Dexian DISYS

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Remote

Contract

Role: Silicon Verification Engineer 2 Location: 100% remote Duration: Till 9/30/2025 (Possible Extension : Yes) Summary: The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans. Job Responsibilities: Define, document, and implement a UVM verification environment including agents and scoreboards Write test plans and implement them by developing tests, test generators, test benches, che

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot