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Design Verification Engineer

Avance Consulting

Mountain View, California, USA

Contract

Job Description Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve issues Execute regressio

Design verification Engineer

Enfycon Inc

Remote or Mountain View, California, USA

Contract

Minimum Qualifications: Design Verification Engineering ServicesTestbench development System Verilog Universal Methodology (UVM), Python, and C testsIntegration/development of C tests/Application Programming Interface (APIs) and software build flowIntegration of UVM testbenchesTest development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage

RTL design Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Job Description: Strong Logic Design, RTL coding (Verilog HDL) and debugging skills Analyze and resolve Lint, CDC and RDC issues in the design Understanding of low power design and validation techniques including UPF Experience with constraint generation, timing closure analysis, formal verification, low power checks using UPF flows and ECO implementation. Experience with writing assertions and doing negative checks to validate assertions Experience with Silicon validation/Bring-up Experience w

Custom SOC IP Verification Engineer

NVIDIA Corporation

Santa Clara, California, USA

Full-time

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions! We are looking for special individuals with desire to deliver innovative products. Together, we will build the next generation of life changing custom SOCs! If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be. This role demands an exper

STAEngineer

Cloudious

San Jose, California, USA

Contract

Position: STA Engineer Location: San Jose CA (Day-1 Onsite) Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus What You'll Be Doing: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficien

Senior ASIC Design Engineer- Emulation (HAPS Engineer)

Cloudious

San Jose, California, USA

Contract

Position: Senior ASIC Design Engineer- Emulation (HAPS Engineer) Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top

ASIC Verification Engineer

AMD (Advanced Micro Devices)

Santa Clara, California, USA

Full-time

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellenc

RTL Engineer

Cloudious

Santa Clara, California, USA

Contract

Title: RTL Engineer Location: Santa Clara, CA (Day-1 onsite) Duration: 6 Months Role: Integrate RISC-V Core to SoC Key Responsibilities Integrate RISC-V CPU cores into SoC designs, collaborating with cross-functional teams (DV, physical design, architecture, verification, and post-silicon validation) to ensure seamless delivery. Develop and optimize RTL (using Verilog/SystemVerilog) for core, interconnect, and memory subsystems. Evaluate and integrate third-party IP, ensuring performance, power,

RTL Engineer: Integrate RISC-V Core to SoC

Intelliswift Software Inc

Santa Clara, California, USA

Contract

Job Title: RTL Engineer: Integrate RISC-V Core to SoC Location(s): Santa Clara, CA - Onsite Must Have skills: 5+ years of experience in RTL design, SoC integration, or related areas.Strong hands-on experience with hardware description languages (Verilog, SystemVerilog, VHDL), EDA tools, and simulators (VCS, NC, Verilator).Deep understanding of SoC design, integration, and high-performance interfaces (e.g., AXI, TileLink, PCIe, Ethernet).Proven ability to debug and optimize designs for functiona

Principal Verification Engineer

OSI Engineering, Inc.

Raleigh, North Carolina, USA

Full-time

A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to help develop cutting-edge technologies that accelerate and secure data. In this full-time role, the Principal Verification Engineer will report to the Director of Design Engineering and take a key role in product development

Principal Verification Engineer

OSI Engineering, Inc.

San Jose, California, USA

Full-time

A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to help develop cutting-edge technologies that accelerate and secure data. In this full-time role, the Principal Verification Engineer will report to the Director of Design Engineering and take a key role in product development

Principal Embedded SWE Image Signal Processing

TESTINGXPERTS, INC. DBA DAMCOSOFT

Denver, Colorado, USA

Full-time, Third Party, Contract

Principal Embedded SWE Image Signal Processing Location: Denver, CO (Hybrid) Key Responsibilities Design, develop, and optimize embedded vision software using Xilinx Kria SOM Develop and integrate with FPGA-based image processing pipelines (ISP) for tasks such as: Demosaicing, noise reduction, white balancing, gamma correction, and image enhancement. Interface with CMOS image sensors (via MIPI CSI-2 or parallel interfaces) and configure them using I2C/SPI. Implement real-time image streaming

Defense Sr. FPGA Design Verification Engineer with Secret Clearance

ZoeTech Staffing LLC

Columbia, Maryland, USA

Full-time

Job Description: Our defense client is seeking digital verification engineers to support our development of secure tactical communication products. The candidate will function primarily in an FPGA verification role, working in a cooperative team environment to verify and test embedded FPGA firmware for radio communication systems. Successful candidates must have familiarity with a coverage-driven verification methodology from planning through closure as well as knowledge of industry standard int

Design Verification Engineer

Mirafra Inc

San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Senior Analog Design Analog Engineer

OSI Engineering, Inc.

Agoura Hills, California, USA

Full-time

A leading chip and silicon IP company is seeking a talented Senior Analog IC Design Engineer to join its Bufferchip Design team in Agoura Hills, California. This is an exciting opportunity to work alongside some of the brightest minds in the industry on innovative products that enhance data speed and security. In this full-time role, the Senior Analog IC Design Engineer will report to the Senior Director of Engineering and play a key role in product definition and design. The position offers hig

Senior Hardware Design Engineer Digital Systems PCB

Paul May & Associates

Saint Charles, Missouri, USA

Full-time

Job Title: Senior Hardware Design Engineer Digital Systems PCB Location: St. Charles, MO (Must be local Hybrid role) Salary: $120K $140K base, depending on experience Employment Type: Full-Time | No relocation or sponsorship Overview: We're hiring a Hardware Design Engineer with strong digital design experience and some analog knowledge. You'll design advanced systems using FPGAs and CPUs, create PCB layouts, and work with power and signal systems. Projects often involve Power over Ethernet (Po

ASIC/SOC Emulation Engineer

INFT Solutions inc

US

Full-time, Part-time, Third Party, Contract

Role: ASIC/SOC Emulation Engineer Work location: Santa Clara, CA. Job Description: "ASIC Emulation Engineer Develop emulation testbenches in System Verilog and/or C/C++. Deliver emulation and prototyping models from RTL on industry standard emulation and prototyping platforms. Build and execute emulation test plan to ensure quality of the models and assist pre-silicon validation. Drive emulation methodologies for HW verification and SW development. Develop emulation tools, workflows, and infras

Silicon Design Engineer

AdientOne LLC

Massachusetts, USA

Contract

Role: Silicon Design Engineer Location: Boxborough MA 01719 | Hybrid Duration: 12+ months The candidate will be a member of the Memory I/O design team designing High Speed IO circuits and implementing DDR IPs. The focus of the activity will be centered around spice simulations and behavior modeling. The supporting team is an established group of talented Analog/Mixed-Signal integrated circuit designers. The site includes the direct supervisor, AMS manager, IP director, and majority of the AMS

Principal Digital Design Engineer

OSI Engineering, Inc.

San Jose, California, USA

Full-time

Principal Digital Design Engineer A premier chip and silicon IP provider focused on accelerating and securing data is seeking an exceptional Principal Digital Design Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This is an exciting opportunity to work alongside some of the industry s most innovative engineers on cutting-edge technology that drives faster and more secure data solutions. In this full-time role, the Principal Digital Design Engineer will report directly to

Clock Distribution Engineer

Tesla Motors

Fort Collins, Colorado, USA

Full-time

The Dojo Hardware team is looking for a Clock Distribution Engineer to work in Fort Collins, CO. This Engineer will be responsible for the design and implementation of clocks at both the SOC and IP level. Responsibilities Design custom clock distribution from PLL to sub-blocks meeting low latency and jitter specs for various SOC clocks Write modular clock RTL to handle changes, integrating it into designStrong tcl knowledge to automate the clock tree generation based on bottoms-up load feedback