ob Title: Senior Verilog Design EngineerJob SummaryWe are looking for a Senior Verilog Design Engineer with 10+ years of experience in RTL design and digital hardware development. The ideal candidate should have strong expertise in ASIC/FPGA design flows, micro-architecture development, and SoC environments, with exposure to PCIe design or verification. Key ResponsibilitiesDevelop and implement RTL using Verilog for ASIC/FPGA platforms. Define micro-architecture and perform RTL coding, simulatio