Search Jobs | Dice.com

Santa Clara, California

•

Today

Job Title: DFx Verification Engineer (DFT Verification) - Semicon companyLocation: Santa Clara, CA (Onsite)Duration: ContractOpen Positions: 15Experience: 4+ Years Role OverviewWe are looking for skilled DFx Verification Engineers with strong experience in Design-for-Test (DFT) verification. The ideal candidate will be responsible for validating DFx features including scan, BIST, JTAG, and low-power test scenarios using SystemVerilog/UVM-based environments. Key ResponsibilitiesDevelop and execut

Easy Apply

Full-time, Third Party

Depends on Experience

DFT / DFx Verification Engineer

Santa Clara, California

•

Today

Key Responsibilities: Develop and execute verification plans for DFx features including: Scan (stuck-at, transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Create and maintain testbenches using SystemVerilog/UVM for DFx validation. Verify: Scan chain integrity and connectivity Test mode functionality and coverage ATPG pattern validation and debug BIST controllers and memory test logic Technical Skills & Expertise: Strong knowledge of DFT/DF

Easy Apply

Third Party, Contract

Depends on Experience

Lead ASIC DFT Engineer

San Jose, California

•

25d ago

Role: Lead ASIC DFT Engineer Location: San Jose, CA (Remote, PST time zone preferred) Work Setup: Remote, PST time zone preferred Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) DFT Architecture definition. Must Full chip / Sub system level DFT activities Must Scan & compression (EDT) implementation Must LBIST implementation and verification any BIST exp is Must Coverage improvements (Spyglass work) Must ATPG Good to Have Role Summar

Easy Apply

Full-time, Contract, Third Party

Depends on Experience

Senior Design for Test (DFT) Engineer

Santa Clara, California

•

Yesterday

Job Title : Senior DFT Engineer Location : Santa Clara, CA Experience : 4+ Years in DFT Skill: [ATPG , MBIST, IO Test, Clock Verification] Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The enginee

Easy Apply

Third Party, Contract

$60 - $70

Sr DFT Engineer (eInfochips Inc)

San Jose, California

•

Today

Position:Sr DFT Engineer (eInfochips Inc) Job Description:WhatYou'llBeDoing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC levelVerify test patterns using gate-level simulations.Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of industry stand

Full-time

DFT Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)

Full-time

USD 81,000.00 - 130,000.00 per year

ASIC DFT Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, throug

Full-time

USD 141,300.00 - 226,000.00 per year

Staff DFT Engineer

Santa Clara, California

•

Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 128,000.00 - 189,370.00 per year

DFT Engineer

Remote

•

Yesterday

3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.

Easy Apply

Contract

Depends on Experience

DFT ENGINEER

Remote

•

11d ago

DFT EngineerMarvell 6 month contract Remote / 3 Top priorities for below role: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFTengineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG,DFTInsertion. Experience with ownDFTVerification. Experience with ICL PDL.

Easy Apply

Contract

70+

Hiring: DFT Lead | 7nm & Below | Saratoga, CA | Full-Time

Saratoga, California

•

15d ago

We re looking for a seasoned DFT Leader to architect and drive test strategy for complex multi-chip SoCs at advanced nodes (7nm and below). Own DFT architecture (Scan, LBIST, MBIST, Memory Repair, OCC, ACJTAG/DCJTAG) Lead ATPG & achieve high @speed scan coverage Hands-on with Synopsys or Mentor test tools Multiple deep submicron tape-outs required SerDes + EMIB exposure is a plus 15+ years semiconductor experience This is a high-impact leadership role shaping next-gen high-performance silicon.

Easy Apply

Full-time

Depends on Experience

Principal DFT Engineer (Silicon Engineering)

Sunnyvale, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 210,000.00 - 295,000.00 per year

DFT - Tessent SSN

Remote

•

13d ago

12+ month contractRemote/3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.

Easy Apply

Contract

60 - 90

DFT Staff Engineer

Santa Clara, California

•

Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

CPU DFT Engineer

Santa Clara, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to ab

Full-time

USD 142,200.00 - 213,400.00 per year

Filter Results

Job post features

Posted date

Work settings

Employment type

Distance

Employer type

Work authorization