"PCIe" jobs in California

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

•

Yesterday

Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ Years Job Type: Contract / Long-Term Job Summary We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP. The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure,

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Full-time, Part-time, Third Party, Contract

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

•

Today

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location :San Jose, CA Experience :10+ yearsPosition SummaryWe are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transcation Layer, Controller, PHY and Serdes. The candidate will be responsible for verification planning, methodology definition, UVM environment architecture, coverage closure, protocol compliance verification, and leadership of a team of verifica

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Third Party, Contract

$90 - $95

Principal / Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration

San Jose, California

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Today

Position :Principal / Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration Location :San Jose, CA Experience :10+ years Job Summary We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely with

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Contract, Third Party

Depends on Experience

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

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10d ago

Hi, Hope you are doing well. We have the position below.Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location: San Jose, CA Duration would be 6 months to start and can be extended to 18 months. Onsite Experience: Lead Verification Engineer: 10+ years Position Summary We are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transcation Layer, Controller, PHY and Serdes. The candidate will be responsible for v

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Contract

60+

Senior ASIC Verification Engineer (PCIe/CXL)

San Jose, California

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing

Full-time

USD 145,600.00 per year

PCIe, CXL and Highspeed IO Validation Engineer

Santa Clara, California

•

Today

Full-time

USD 170,100.00 per year

PCIe Validation Engineer

Santa Clara, California

•

Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team, we'd l

Full-time

USD 159,000.00 - 239,000.00 per year

PCIe System Architect/ Principal Engineer-18290

Sunnyvale, California

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Today

Descriptions & Requirements Job Description and Requirements We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are You are PCIe/CXL Syst

Full-time

Verification Engineer in CA and TX

San Francisco, California

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Today

Hi, I hope all is well. I am doing a search for a client who has an urgent requirement for a network administrator contract opportunity. The job description is listed below. If this is something you are interested in, please call me ASAP at . please mail me your updated resume in Word format, availability, contact details, and hourly rate as per the hiring policy of our client. ASIC Verification Engineer About the role: PCIe Protocol IP Verification Expert: Consulting & Turnkey projec

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Third Party, Contract

Depends on Experience

Emulation Engineer

Remote or California

•

Yesterday

Senior Emulation Engineer Location: San Jose, CA (Remote) Experience: 10+ Years We are hiring an experienced Senior Emulation Engineer with strong expertise in Siemens Veloce, Cadence Palladium, or Synopsys ZeBu. Required Skills: Hands-on experience with Veloce, Palladium, or ZeBu emulation platforms Experience with FPGA prototyping (HAPS, Protium, or proFPGA) Strong knowledge of PCIe, UCIe, LPDDR, and HBM Solid understanding of SoC architecture, RTL (Verilog/SystemVerilog), and digital des

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Full-time, Part-time, Contract, Third Party

Sr. Emulation Engineer

San Jose, California

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11d ago

Job Title: Sr. Emulation Engineer Location: San Jose, CA (Onsite) Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platformsAdapt SoC designs for Emulation and PrototypingDevelop and debug emulation testbenches and system-level environmentsSupport pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and valid

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Third Party, Contract

Depends on Experience

Silicon Validation Engineer

Santa Clara, California

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19d ago

Job Description:We are looking for aSiliconValidationEngineerwith experience in hardwarevalidationand board bring-up. The ideal candidate should have hands-on experience in lab environments, debugging hardware issues, and validatingsiliconplatforms.Key Responsibilities:Perform board bring-up, hardware debugging, andvalidationactivities.Execute board testing according to defined test plans.Perform electrical measurements on various I/O interfaces such as PCIe, USB, HDMI, I2C, and SPI.Use lab equi

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Contract, Third Party

40 - 45

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

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11d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

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Contract

90 - 130

Principal Product Application Engineer - PCIe

San Jose, California

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Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 170,500.00 - 220,000.00 per year

System Design Test Engineer - Cupertino, CA

Cupertino, California

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Today

Job Title: System Design Test Engineer Location: Cupertino, CA Onsite/ Remote: Onsite Duration: 6+ months contract Sample resume atached System Design & Test Engineer As a system design & test engineer, you will be responsible for designing hardware to validate board level system functionality and electrical performance of new Apple products. This position is a great fit for someone who is passionate about designing hardware, and working cross-functionally with teams across Apple (design, firm

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Contract

Depends on Experience

Sr. System Hardware Design Engineer

Milpitas, California

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3d ago

Job Title: Sr. System Hardware Design Engineer (High Speed Design) Location: Milpitas, CA Duration: 12 months + possible contract to hire beyond a year Ideal Start Date: 8/31/2026 Work Schedule: 5 days a week onsite US Persons Only Background Check and Drug Screen Both Required Project Details: Our client is seeking a Senior System Hardware Design Engineer to support the development of next-generation high-speed embedded hardware platforms. This role will be responsible for the complete hardwa

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Contract

$70 - $85

PCIe Software Engineer

Santa Clara, California

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Today

Company Description Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital la

Full-time

USD 123,000.00 - 191,000.00 per year

PCIe Senior/Lead Software Engineer

Santa Clara, California

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Today

Full-time

USD 140,000.00 - 210,000.00 per year

Director Applications Engineering PCIE

Sunnyvale, California

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Today

Descriptions & Requirements Job Description and Requirements Open to hiring for this role to be located in either Austin or Sunnyvale We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future

Full-time

NVME Test Engineer_Sanjose, CA (Onsite)_Only Xoriant W2

San Jose, California

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13d ago

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE:- NVME Test Engineer LOCATION Sanjose, CA (Onsite) DURATION 12+ Months (May get extend) MODE OF INTERVIEW Zoom/Webex/Onsite RATE $75 per hour on w2 (without Benefits) JOB DESCRIPTION This position will define, implement and support

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Contract

$60 - $75

"PCIe" jobs in California, USA