Entry Level Physical Design Engineer jobs

Physical Design Engineer (PnR / PPA / Timing Closure) - Austin TX

Texas

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Yesterday

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closu

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Full-time

Physical Design Engineer with (PnR), (PPA) and timing convergence - Austin TX

Texas

•

Yesterday

job Description - Physical Design Engineer with (PnR), (PPA) and timing convergence - Austin TX We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optim

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Full-time

Physical design Engineer

Mountain View, California

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Yesterday

Position 1 Physical Design Engineer Mountain View CA (onsite - Hybrid) Mode of hiring: Fulltime permanent Customer wants someone who is having some logical design experience along with PD experience. Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred. Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization Provides services in transforming the RTL d

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Full-time

$120,000 - $140,000

Physical Design Engineer

Remote

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Today

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

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Contract, Third Party

$60+

Physical Design Engineer

Palo Alto, California

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Today

Job Title: Physical Design Engineer Location: Palo Alto, CA // Onsite Only local candidates allowed Duration: 6-12+ Months Contract Job Description: Exposure to TSMC 2NP/3NP is must Perform endtoend physical design flow: FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations Handle lowpower design techniques: MultiVt, Multivoltage (UPF

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Contract, Third Party

80 - 85

Physical Design Engineer

Austin, Texas

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28d ago

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Full-time

Depends on Experience

Physical Design Engineer

Palo Alto, California

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2d ago

Title: Physical Design Engineer Location: Palo Alto, CA (Full Onsite) Employment Eligibility Statement Due to specific project and client requirements, this position is open to U.S. Citizens and U.S. Lawful Permanent Residents (s) . Sponsorship is not available at this time. Danta Technologies evaluates all candidates in compliance with the Immigration and Nationality Act (INA) and EEOC guidelines . All hiring decisions are made without regard to race, color, religion, sex, gender identity, sex

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Contract

Physical Design Engineer

Palo Alto, California

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Yesterday

Location: Palo Alto, CA (Full Onsite) Exposure to TSMC 2NP/3NP is must Perform endtoend physical design flow: oFloorplanning oPower planning (PG grid, IR) oPlacement & optimization oCTS (Clock Tree Synthesis) oRouting oPostroute optimization Achieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations Handle lowpower design techniques: oMultiVt, Multivoltage (UPF) oPower gating, clock gating Perform physical verification and signoff: oSTA (Primetime) oSI / Cro

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Contract

Depends on Experience

Physical Design Engineer

Palo Alto, California

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2d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

Physical Design Engineer – Lead

San Jose, California

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2d ago

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

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Full-time

Depends on Experience

Physical Design Engineer

San Jose, California

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Yesterday

Job Title: Physical Design Engineer Location: San Jose CA We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Thanks & Regards.., Abishek B Reveille Technologies, Inc

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Contract

Depends on Experience

Physical Design Engineer

San Francisco, California

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10d ago

Physical Design EngineerBay Area, CABelow is the Job Description:Good understanding of Cadence tools (Innovous, Quantus, Voltus).Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.Experience in developing and implementing Power-grid and high speed clock constraints and specifications.Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.Experience with CDC, stati

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Contract

65 - 75

Physical Design Engineer

San Jose, California

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30+d ago

Job Title: Physical Design Engineer Location: San Jose CA Contract We are seeking a Physical Design contractor with strong synthesis and implementationexpertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designsDrive PPA (power, performance, area) optimization through synthesis and earlyimplementation stages. Develop and refine floorplans using Cadence InnovusCollaborate c

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Third Party, Contract

$60 - $80

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

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Today

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

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Full-time

Depends on Experience

ASIC Physical Design Engineer

Lafayette, Indiana

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22d ago

Were hiring for a full-time opportunitywith a leading semiconductor end client in Lafayette, IN. Seeking experienced ASIC Physical Design / Backend Engineers with strong TSMC FinFET tapeout and signoff experience.. Detailed job description is given below. Title:ASIC Physical Design Engineer (TSMC / FinFET) Location: Lafayette, Indiana (Relocation assistance provided) Type: Full time with Client Tapeout , Signoff , DRC/LVS/PEX,Customer interaction Job Responsibilities: Act as the primary inter

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Full-time, Third Party

Depends on Experience

Urgent Opening for Priority | Physical Design Engineer - Lead

Remote

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Yesterday

Priority: Physical Design Lead Position: Physical Design Engineer Lead What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional teams to resolve im

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Contract

Depends on Experience

HBM SoC Physical Design Engineer

Richardson, Texas

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work cl

Full-time

Entry Level Mechanical Design Engineer

San Diego, California

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Today

Move Forward with Volt! Volt is immediately hiring for an Entry Level Mechanical Design Engineer in San Diego, CA. As an entry level Mechanical Design Engineer, you will: Create and maintain the Mechanical and Systems composite product design Can cover one or more of composite disciplines; electrical, hydro-mechanical, controls manufacturing, software and display, This position is aimed at the maintenance of Mechanical and Hydro-Mechanical product design This is a Full-Time Temp to Hire opportun

Full-time

USD 30.00 - 32.00 per hour

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

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Today

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.Be part of Amazon Leo?s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with cus

Full-time

Physical Design Engineer II (IC)

San Jose, California

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Today

Position:Physical Design Engineer II (IC) Job Description:What candidate will Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively ide

Full-time