SystemVerilog jobs

Design Verification Engineer – UVM/SystemVerilog

San Jose, California

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9d ago

Job SummaryWe are seeking an experienced Design Verification (DV) Engineer to join our Interface IP Design Verification team. The ideal candidate will have strong hands-on experience in SystemVerilog and UVM-based verification, along with expertise in validating complex IP subsystems and standard interface protocols. You will collaborate closely with architects, RTL designers, integration teams, and external IP vendors to ensure functional correctness, performance, and compliance with architectu

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Contract

Depends on Experience

DFX/DFT Engineer

Santa Clara, California

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Today

DFX/DFT Engineer Location : Bay area CA Experience :- 6 to 8 yrs Onsite 6-12 months JD:- We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality. Key Responsibilities Create and execute test plans for DF

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Contract

Depends on Experience

RTL Verification Engineer # 26-21738

Ben Lomond, California

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6d ago

Duration: 12+ Months About the role:Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-ra

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Contract

$80 - $85

Design Verification Engineer

San Jose, California

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6d ago

NMK Global Inc.is a global IT Services & Solutions company specializing in IT Staffing, Technology Consulting, Workforce Solutions, and Application Development Services. We help organizations build high-performing technology teams by connecting them with exceptional talent across a wide range of industries. Our expertise, industry knowledge, and consultative approach enable clients to achieve successful business outcomes while helping professionals advance their careers. Job Title: Design Ver

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Contract, Third Party

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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2d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

RTL Verification Engineer # 26-23383

Markham, Ontario

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6d ago

Duration: 8 months Description: As a Verification Engineer 5, you will play a key role in defining, developing, and executing advanced verification solutions for complex Display IP and SoC designs. You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market. The ideal candidate is passionate about verification methodologies, possesses strong expertise in System Verilog/UVM-based ver

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Contract

$80 - $100

Design Verification Engineer

Remote

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Yesterday

Job SummaryWe are seeking a motivated Design Verification Engineer with 13 years of experience in digital design verification and semiconductor engineering. The candidate will work with RTL design and verification teams to develop testbenches, execute simulation-based verification, debug design issues, and validate the functionality and reliability of digital designs. The ideal candidate should have hands-on knowledge of Verilog, SystemVerilog, digital logic design, and verification methodologie

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Full-time

75000 - 100,000

Formal Verification

Ben Lomond, California

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9d ago

JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run du

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Third Party, Contract

Depends on Experience

Mixed Signal Verification Engineer _San Jose, CA (Onsite, Only local Candidates)

San Jose, California

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Today

TITLE:-Mixed Signal Verification Engineer LOCATION San Jose, CA DURATION 12+ Months (High possibility of Extension) MODE OF INTERVIEW Zoom/Webex/Onsite RATE $150 per hour on W2 (Without benefits) JOB DESCRIPTION JOB RESPONSIBILITIES Creating AMS/DMS testbench for wireless RF and High Speed PHY. Working with RF/Analog design engineers for analog circuit models Support silicon bring-up and commercialization. REQUIRED SKILLS BS or BE minimum, 3+ year experiences Deep understanding of digital VL

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Contract

120 - 150

CPU Verification ML Tool Engineer

Santa Clara, California

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Today

In this highly visible role, you will be at the center of a chip design effort interfacing with many disciplines, with a critical impact on getting high quality products to millions of customers quickly. Description As a CPU verification ML tool engineer owning the ML based verification tools, and flow of a high performance lower power processor design, you will have the responsibilities as follows: Work closely with verification engineers and RTL designers on defining effective ML based veri

Full-time

Mixed Signal Verification Engineer

Austin, Texas

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Today

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardwa

Full-time

Digital/Mixed Signal Modeling/Verification Engineer

Austin, Texas

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Today

Full-time

DFT (Design for Test) Engineer_SanJose, CA (Onsite)

San Jose, California

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Today

Design for Test (DFT) Engineer Location: San Jose, CA Duration: 12 + Months (Potential Extension) Interview Process: Virtual/Onsite Rate: Up to $130/hr on W2 (No Benefits) Job OverviewWe are seeking an experienced Design for Test (DFT) Engineer to support the development and validation of next-generation semiconductor products. The role involves close collaboration with Front-End Design and Physical Design teams to implement and optimize DFT solutions for advanced wireless and connectivity c

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Contract

100 - 130

DV Engineer

Dallas, Texas

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Today

Strong System Verilog/UVM knowledge with practical experience on live projectsExpertise in AMBA bus protocols, ARM CPU, and experience in PCI Express and/or Ethernet bus protocols (desirable)Proficiency in Unix, Configuration Management, Bug tracking, and verification dashboarding toolsExperience in developing functional verification environments, including components like monitors, checkers, scoreboards, and assertions, along with knowledge of verification methodologies using random stimulus an

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Third Party, Contract

Depends on Experience

DFT Engineer

San Jose, California

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29d ago

DFT EngineerIntroduction:The DFT Engineer position at Sivaltech Inc involves working on ASIC/SoC designs, implementing Design for Testability (DFT) techniques, and ensuring the efficient testing of semiconductor devices. The role requires expertise in DFT tools, verification, testing, and debugging to support the overall product development lifecycle. Responsibilities:Implement DFT strategies for ASIC/SoC designsWork on Scan, JTAG, BIST, and MBIST techniquesGenerate test patterns and verify DFT

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Contract, Third Party

Depends on Experience

Mixed Signal Verification Engineer

San Jose, California

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Today

Job Description ONSITE in San Jose, CA JOB RESPONSIBILITIES Creating AMS/DMS testbench for wireless RF and High Speed PHY. Working with RF/Analog design engineers for analog circuit models Support silicon bring-up and commercialization. REQUIRED SKILLS BS or BE minimum, 3+ year experiences Deep understanding of digital VLSI simulation flow Deep understanding of mixed-mode and analog simulation flow Experience with Verilog/SystemVerilog and RNM modeling Experience with digital verification, U

Contract

Verification Engineer

Austin, Texas

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Today

Job Description Description: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) Strong proficiency in System Verilog Assertions (SVA) and formal property specification Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis Familiarity with scripting languages (TCL, Python, Perl) for flow automation Extensive experience in design verification with a strong focus on formal verificatio

Full-time

Analog Mixed Signal Firmware Engineer

Cupertino, California

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Today

Imagine what you could do here at Apple? Together we could help craft the next generation of the world's finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. The team is searching for a self-motivating, passionate electrical engineer for the role of AMS Firmware Engineer. As a team, we will be working on the leading-edge technology no

Full-time

ASIC/SoC Verification Architect – Short Supplier

St. Louis, Missouri

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24d ago

Key Requirements: 10+ years of experience in ASIC/SoC verification and verification architecture. Strong hands-on SystemVerilog, UVM, Verilog, and constrained-random verification. Experience developing verification strategies, test plans, testbenches, coverage models, and verification environments. Strong knowledge of SoC architecture, RTL, CPU/processor, interconnects, memory, and IP verification. Experience with UVM/SystemVerilog assertions, functional/code coverage, simulation, and debugging.

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Contract

Up to 160

Sr. Design Verification Engineer || San Jose, CA

San Jose, California

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Today

Sr. Design Verification Engineer Location: San Jose, CA ( Onsite ) Facet to face interview is a must after Video call. Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ab

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Third Party, Contract

Depends on Experience