UVM jobs in Remote

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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9d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

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Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

9d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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2d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

Design Verification Engineer – UVM/SystemVerilog

San Jose, California

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9d ago

Job SummaryWe are seeking an experienced Design Verification (DV) Engineer to join our Interface IP Design Verification team. The ideal candidate will have strong hands-on experience in SystemVerilog and UVM-based verification, along with expertise in validating complex IP subsystems and standard interface protocols. You will collaborate closely with architects, RTL designers, integration teams, and external IP vendors to ensure functional correctness, performance, and compliance with architectu

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Contract

Depends on Experience

Design Verification Engineer

San Jose, California

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6d ago

NMK Global Inc.is a global IT Services & Solutions company specializing in IT Staffing, Technology Consulting, Workforce Solutions, and Application Development Services. We help organizations build high-performing technology teams by connecting them with exceptional talent across a wide range of industries. Our expertise, industry knowledge, and consultative approach enable clients to achieve successful business outcomes while helping professionals advance their careers. Job Title: Design Ver

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Contract, Third Party

Depends on Experience

RTL Verification Engineer # 26-21738

Ben Lomond, California

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6d ago

Duration: 12+ Months About the role:Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-ra

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Contract

$80 - $85

Design Verification Engineer

San Jose, California

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6d ago

Location : Bay area (San Jose) CA Onsite Duration : Long term Locals We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges

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Contract

Depends on Experience

RTL Verification Engineer

Santa Clarita, California

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19d ago

RTL Verification Engineer System Verilog, UVM Good knowledge in AMBA,AX4,AHB IP/SS/SOC verification experience Test Env, test case development Regression debug, coverage analysis Good knowledge in One of the High speed IF protocol like PCIe6, DDR5, Ethernet or USB3 Experience in Synopsys/Cadance Tools usage

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Third Party, Contract

$55 - $57

ASIC Verification Engineer

Allentown, Pennsylvania

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Today

Role: ASIC Verification Engineer (only w2 candidate)Location: 100% onsite at Cisco office in either :Allentown PA office or Carlsbad CA officeDuration: CTHBasic QualificationsBachelor's degree in Electrical Engineering or a related field.UVM Based testbench development.Experience in ASIC or SOC verification.Demonstrated experience in developing test plans and verification infrastructure.Practical knowledge of verification methodologies from block level to system level.Proficiency in System Veri

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Contract, Third Party

$65 - $70

Verification Engineer

Sunset Valley, Texas

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9d ago

Job Description: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) Strong proficiency in System Verilog Assertions (SVA) and formal property specification Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis Familiarity with scripting languages (TCL, Python, Perl) for flow automation Extensive experience in design verification with a strong focus on formal verification Expertise i

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Contract, Third Party

Depends on Experience

RTL Verification Engineer # 26-23383

Markham, Ontario

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6d ago

Duration: 8 months Description: As a Verification Engineer 5, you will play a key role in defining, developing, and executing advanced verification solutions for complex Display IP and SoC designs. You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market. The ideal candidate is passionate about verification methodologies, possesses strong expertise in System Verilog/UVM-based ver

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Contract

$80 - $100

DV Engineer

Dallas, Texas

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Today

Strong System Verilog/UVM knowledge with practical experience on live projectsExpertise in AMBA bus protocols, ARM CPU, and experience in PCI Express and/or Ethernet bus protocols (desirable)Proficiency in Unix, Configuration Management, Bug tracking, and verification dashboarding toolsExperience in developing functional verification environments, including components like monitors, checkers, scoreboards, and assertions, along with knowledge of verification methodologies using random stimulus an

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Third Party, Contract

Depends on Experience

Mixed Signal Verification Engineer _San Jose, CA (Onsite, Only local Candidates)

San Jose, California

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Today

TITLE:-Mixed Signal Verification Engineer LOCATION San Jose, CA DURATION 12+ Months (High possibility of Extension) MODE OF INTERVIEW Zoom/Webex/Onsite RATE $150 per hour on W2 (Without benefits) JOB DESCRIPTION JOB RESPONSIBILITIES Creating AMS/DMS testbench for wireless RF and High Speed PHY. Working with RF/Analog design engineers for analog circuit models Support silicon bring-up and commercialization. REQUIRED SKILLS BS or BE minimum, 3+ year experiences Deep understanding of digital VL

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Contract

120 - 150

Verification Engineer

Austin, Texas

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Yesterday

Job Description Description: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) Strong proficiency in System Verilog Assertions (SVA) and formal property specification Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis Familiarity with scripting languages (TCL, Python, Perl) for flow automation Extensive experience in design verification with a strong focus on formal verificatio

Full-time

Mixed Signal Verification Engineer

San Jose, California

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Today

Job Description ONSITE in San Jose, CA JOB RESPONSIBILITIES Creating AMS/DMS testbench for wireless RF and High Speed PHY. Working with RF/Analog design engineers for analog circuit models Support silicon bring-up and commercialization. REQUIRED SKILLS BS or BE minimum, 3+ year experiences Deep understanding of digital VLSI simulation flow Deep understanding of mixed-mode and analog simulation flow Experience with Verilog/SystemVerilog and RNM modeling Experience with digital verification, U

Contract

Design Verification Engineer

Remote

•

Yesterday

Job SummaryWe are seeking a motivated Design Verification Engineer with 13 years of experience in digital design verification and semiconductor engineering. The candidate will work with RTL design and verification teams to develop testbenches, execute simulation-based verification, debug design issues, and validate the functionality and reliability of digital designs. The ideal candidate should have hands-on knowledge of Verilog, SystemVerilog, digital logic design, and verification methodologie

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Full-time

75000 - 100,000

Senior FPGA Engineer

El Segundo, California

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Today

Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products. Develops high-level and detailed designs consistent with requirements and specifications. Validates designs through various methods of review, testing and analysis. Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements. Supports Supplier Management with make/buy recommendations and oth

Full-time

ASIC/SoC Verification Architect – Short Supplier

St. Louis, Missouri

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24d ago

Key Requirements: 10+ years of experience in ASIC/SoC verification and verification architecture. Strong hands-on SystemVerilog, UVM, Verilog, and constrained-random verification. Experience developing verification strategies, test plans, testbenches, coverage models, and verification environments. Strong knowledge of SoC architecture, RTL, CPU/processor, interconnects, memory, and IP verification. Experience with UVM/SystemVerilog assertions, functional/code coverage, simulation, and debugging.

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Contract

Up to 160

IC Verification Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.Architect and develop scalable and re-usable test benches, using the framework of the verification methodologyBuild pseudo-rando

Full-time

USD 121,900.00 - 195,000.00 per year

Sr. Design Verification Engineer || San Jose, CA

San Jose, California

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Today

Sr. Design Verification Engineer Location: San Jose, CA ( Onsite ) Facet to face interview is a must after Video call. Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ab

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Third Party, Contract

Depends on Experience