Uvm jobs in remote

Senior Emulation/Verification Engineer In Bay Area, CA || Hybrid Role

Hybrid in Menlo Park, California

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Today

Role: Senior Emulation/Verification EngineerDuration: Long TermLocation: Bay Area, CA || Hybrid Role Job Description-: We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

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Contract

Depends on Experience

Verification Engineer

Sunnyvale, California

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5d ago

Hello, Hope you are doing well. Title: ARM IP Verification Engineer Location: Sunnyvale, CA Are you passionate about building robust verification environments for next-gen silicon? We are looking for an experienced ARM IP-Level Verification Engineer to join our team in Sunnyvale, CA. If you thrive on architecting complex UVM testbenches, driving coverage closure, and developing custom VIP from the ground up, we want to hear from you. Key Focus Areas: SystemVerilog & UVM mastery Custom VIP de

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Contract

50 - 60

Senior Staff Verification Consultant

Austin, Texas

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Today

Job Title: Senior Staff Verification Consultant Location: Austin, TX (Onsite, 5 days/week) Duration: Long Term Only W2 //NO CORP TO CORP// Description As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block

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Contract

85 - 95

SoC Verification Engineer - NoC / UVM

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

SoC Design Verification Engineer

San Jose, California

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3d ago

Position Title: SoC Design Verification Engineer Location: San Jose, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute S

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Full-time, Third Party

Depends on Experience

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

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Yesterday

Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ Years Job Type: Contract / Long-Term Job Summary We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP. The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure,

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Full-time, Part-time, Third Party, Contract

Design Verification Engineer

San Jose, California

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19d ago

Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required 8+ years of Design Verification experience in s

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Contract

Depends on Experience

Sr. Asic Design Verification Engineer

Hybrid in Austin, Texas

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6d ago

Job Title: Senior ASICDesignVerificationEngineerLocation:Austin, TX (Onsite/Hybrid) Experience:15+ YearsJob SummaryWe are seeking an experiencedSenior ASICDesignVerificationEngineerto verify next-generation CPU, AI/ML,andSoCdesigns. The ideal candidate will have strong expertise in developingUVM-basedverificationenvironments, functional coverage, RTL debug,andconstrained-randomverificationwhile working closely withdesignandarchitecture teams from specification through tape-out.Primary Skills (Mu

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Third Party, Contract

Depends on Experience

Design Engineer

Sunnyvale, California

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10d ago

Payrate: $82.00- $85.00/hr. Summary Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement. ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performan

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Third Party, Contract

$82 - $85

Design Verification Engineer

Remote

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5d ago

Hi - Full Time Role Job Title: Design Verification Engineer -Performance Modelling Location : Remote USA Strong understanding of SV and UVM and good debugging skills.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely wi

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Full-time

Depends on Experience

FPGA Engineer

Melbourne, Florida

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Today

Required Skills: Expert-level verification engineer with strong SystemVerilog and/ or UVM experience orFPGA verification in lab testing and/or Hardware FPGA design verification testingExperience with design on Xilinx products would be a strong plusexpected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team. Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VH

Full-time

ASIC Emulation Engineer

San Jose, California

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19d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

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Contract

60 - 75

Design Verification Engineer (Only W2)

Santa Clara, California

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Today

Job descriptionYour Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers'' specifications whether they''re a major telecom organization or automotive company, etc. What You Can Expect As a leading member of the Network S

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Full-time

150,000 - 300000

Senior Emulation Engineer

San Jose, California

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Today

We have an open Emulation Engineer position in San Jose, USA. Senior Emulation Engineer Location: San Jose, CA Exp: 10+ years Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software br

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Third Party, Contract

Depends on Experience

ASIC/FPGA Verification Engineer 5

El Segundo, California

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Today

This posting is for a contract assignment and is not a full-time employment offer with Boeing. Candidates selected for roles will be employed as contract workers through a Boeing approved 3rd party for the duration of the specified project. Regular and predictable attendance is required Work statement is a non-managerial role, non-leadership role. Resolves complex issues on critical programs related to architectural approaches, requirements, specifications and design. Leads technical aspect of p

Full-time

Design Verification Engineer

Remote

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6d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

Depends on Experience

Plant Operations Director

Middlebury, Vermont

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Today

Job Description\n Please submit cover letter and resume for consideration. \n Job Summary: \n The Plant Operations Director has overall departmental leadership responsibilities for building maintenance, Biomed and Hazardous Waste for all PMC locations and Helen Porter. The Plant Ops Director is responsible for the planning, organizing, directing and supervising assigned activities of the Engineering/Maintenance Department functions in maintaining the physical structures, Life Safety Codes, comp

Full-time

Senior Staff Verification Consultant

Austin, Texas

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Today

Job Description Onsite in Austin, TX or San Jose, CA - 5 days a week Description As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role. Key r

Contract

Design Engineer III

Sunnyvale, California

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Today

Job Description Onsite 3 days in Sunnyvale, CA Job Description About the role: Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement. Responsibilities Develop and execute verification plans for RTL blocks/IPs across the subsystem. Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests. Drive functional coverage and assertion (SVA) closure; run a

Contract

USD 80.00 - 86.00 per hour

FPGA Engineer

Tucson, Arizona

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Today

JOB TITLE: FPGA ENGINEER JOB LOCATION: TUCSON, AZ WAGE RANGE*: 105.00-110.00 PER HOUR JOB NUMBER: RTXCJP00001415 REQUIRED EXPERIENCE: Minimum 5-8 years of experience to include at least 1 of the following: Digital design and VHDL coding Xilinx or Microsemi devices and flow tools Delivering FPGA solutions to system level applications Hands on experience with integration and debug SECRET CLEARANCE JOB DESCRIPTION FPGA Engineers develop and verify designs for all major FPGA vendors and devi

Full-time