Search Jobs | Dice.com

California

•

5d ago

Job Description The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating c

Full-time

DFT Engineer

Santa Clara, California

•

19d ago

Job Title: DFT Engineer Location: Santa Clara, CA Role Purpose: We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key Responsibilities:Work on Scan insertion, ATPG, GLS (timing/non-timing)Implement MBIST and/or Boundary Scan (BSCAN, JTAG)Support DFT architecture and chip-level integrationDebug DFT issues and improve test coverage Requirements:Experience in at least 2 DFT areas (Scan/ATPG/MBIST/BSCAN/GLS)Strong understanding of DFT concepts and flowExp

Easy Apply

Third Party, Contract

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

Today

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Job Description Key skills for Lead ASIC DFT: please see these key words of in the project description for the profile consideration. SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer

Easy Apply

Full-time, Part-time, Third Party, Contract

ASIC DFT Engineer

Rockford, Illinois

•

3d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Type :- */W2 Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

Easy Apply

Full-time, Third Party

Depends on Experience

Lead ASIC DFT Engineer

No location provided

•

Today

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Any Visa Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-sil

Easy Apply

Contract

Lead ASIC DFT Engineer

Remote

•

17d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

Easy Apply

Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

2d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Rate $100/hr C2C Any Visa Job Description 10+ years of hands-on experience in ASIC Design-for-Test (DFT) please see these key words of in the project description for the profile consideration. SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax

Easy Apply

Third Party, Contract

Depends on Experience

DFT Engineer

San Jose, California

•

23d ago

Role :- Senior ASIC DFT CDC Constraints Eng Location :- San Jose, CA/Milpitas, CA (Remote) Type :- */W2 This is a highly specialised role at the intersection of Design for Test (DFT) architecture and clock domain crossing (CDC) constraint engineering. The successful candidate will own the SDC/SSTA constraint strategy that governs both functional timing closure and DFT scan-mode operation across a complex multi-clock SoC. You will work daily at the boundary where CDC violations manifest as sca

Easy Apply

Full-time, Third Party

Depends on Experience

Senior DFT / ATPG Engineer

Santa Clara, California

•

2d ago

Job Title: DFT / ATPG Engineer Location:Santa Clara, CA (Onsite) Duration: 12+ Months Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with crossfunctional teams to enab

Easy Apply

Contract, Third Party

55 - 60

DFT Engineer

Remote

•

10d ago

3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.

Easy Apply

Contract

Depends on Experience

DFT Engineer

Santa Clara, California

•

9d ago

Familiarity with the Siemens suite of DFT toolsDFT insertion for SCAN (with SSN) and MBISTMBIST Repair Implementation and VerificationGenerating collaterals for Test Timing and Place and RouteExpertise in IJTAG 1687 standard and good at understanding ICL and PDL standard SpecVerification of DFT features, includingBoundary ScanJTAGSCANMBISTHigh Speed IO

Easy Apply

Full-time

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

5d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Duration - Contract Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundar

Easy Apply

Third Party, Contract

$75 - $80

Lead ASIC DFT Engineer

Remote

•

11d ago

Job Description Role:Lead ASIC DFT Engineer Location: Remote(must be aligned with PST time zone) Role Summary We are seeking a highly experiencedLead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resoluti

Easy Apply

Full-time

70 - 75

Lead ASIC DFT Engineer

Remote

•

3d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of cri

Easy Apply

Contract, Third Party

$70 - $90

Sr DFT Engineer

Santa Clara, California

•

2d ago

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin

Easy Apply

Third Party, Contract

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

3d ago

Role: Lead ASIC DFT Engineer Location Remote preferred PST otherwise anywhere in USA Duration: 12+ month contract Job Description Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutio

Easy Apply

Contract

Depends on Experience

DFT Engineer

Remote

•

26d ago

Contract role. 12 months Remote 3 Main priorities below: 1- Tile Based Approach 2-TessentSSN- specificallySSN 3- MCM Packages/Die-To-Die ChipsDFT engineer- Expert with Tessent tools. Experience with TessentSSN. Experience working on ATPG, MBIST, JTAG,DFTInsertion. Experience with ownDFTVerification. Experience with ICL PDL.

Easy Apply

Contract, Third Party

60 - 90

SoC DFT Engineer

Austin, Texas

•

5d ago

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the techn

Full-time

Lead ASIC DFT Engineer

Remote

•

2d ago

Job Title: Lead ASIC DFT EngineerLocation: Remote (PST time zone)Duration: 12 Months Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary:We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This

Easy Apply

Third Party, Contract

Depends on Experience

Principal DFT Engineer

Austin, Texas

•

5d ago

DFT Engineer You will join a team working on leading-edge projects in the Business Unit (BU) MCU & MPU Engineering & Design Enablement (MMEDE). MMEDE BU brings the technology and ecosystem relationships for next gen automotive Processing, Edge Processing & Radar Processing products. Your Responsibilities: Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.Inserting of MBIST RTL for memories & Verifying them.Analyzing Scan DRCs & fixing them in RTL.Analyzing

Full-time

Filter Results

Job post features

Posted date

Work settings

Employment type

Distance

Employer type

Work authorization