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Santa Clara, California

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Yesterday

Job Title : Senior DFT Engineer Location : Santa Clara, CA Experience : 4+ Years in DFT Skill: [ATPG , MBIST, IO Test, Clock Verification] Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The enginee

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Third Party, Contract

$60 - $70

Lead ASIC DFT Engineer

San Jose, California

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25d ago

Role: Lead ASIC DFT Engineer Location: San Jose, CA (Remote, PST time zone preferred) Work Setup: Remote, PST time zone preferred Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) DFT Architecture definition. Must Full chip / Sub system level DFT activities Must Scan & compression (EDT) implementation Must LBIST implementation and verification any BIST exp is Must Coverage improvements (Spyglass work) Must ATPG Good to Have Role Summar

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Full-time, Contract, Third Party

Depends on Experience

Sr DFT Engineer (eInfochips Inc)

San Jose, California

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Today

Position:Sr DFT Engineer (eInfochips Inc) Job Description:WhatYou'llBeDoing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC levelVerify test patterns using gate-level simulations.Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of industry stand

Full-time

DFT Engineer

Remote

•

Today

3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.

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Contract

Depends on Experience

DFT ENGINEER

Remote

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11d ago

DFT EngineerMarvell 6 month contract Remote / 3 Top priorities for below role: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFTengineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG,DFTInsertion. Experience with ownDFTVerification. Experience with ICL PDL.

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Contract

70+

Design For Test (DFT) Engineer

Remote

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20d ago

5+ years of SoC-level front-end integration experience Strong background in multi-IP subsystem assembly and third-party IP integrationExperience configuring and integrating NoC / interconnect fabricsGeneral DFT awareness at the SoC integration levelComfortable working cross-functionally with verification, physical design, and DFT teamsProficiency in Verilog / SystemVerilog

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Third Party, Contract

Depends on Experience

DFT / DFx Verification Engineer

Santa Clara, California

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Today

Key Responsibilities: Develop and execute verification plans for DFx features including: Scan (stuck-at, transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Create and maintain testbenches using SystemVerilog/UVM for DFx validation. Verify: Scan chain integrity and connectivity Test mode functionality and coverage ATPG pattern validation and debug BIST controllers and memory test logic Technical Skills & Expertise: Strong knowledge of DFT/DF

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Third Party, Contract

Depends on Experience

DFT Verification Engineer

Santa Clara, California

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Today

Job Title: DFx Verification Engineer (DFT Verification) - Semicon companyLocation: Santa Clara, CA (Onsite)Duration: ContractOpen Positions: 15Experience: 4+ Years Role OverviewWe are looking for skilled DFx Verification Engineers with strong experience in Design-for-Test (DFT) verification. The ideal candidate will be responsible for validating DFx features including scan, BIST, JTAG, and low-power test scenarios using SystemVerilog/UVM-based environments. Key ResponsibilitiesDevelop and execut

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Full-time, Third Party

Depends on Experience

DFT Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)

Full-time

USD 81,000.00 - 130,000.00 per year

ASIC DFT Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, throug

Full-time

USD 141,300.00 - 226,000.00 per year

Principal SoC DFT Engineer, HBM

Richardson, Texas

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chi

Full-time

USD 146,000.00 - 309,000.00 per year

ASIC DFT Engineer

Fort Collins, Colorado

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, thro

Full-time

USD 108,000.00 - 172,800.00 per year

Staff DFT Engineer

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 128,000.00 - 189,370.00 per year

DFT Engineer (Design for Testability) - Staff

Richardson, Texas

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is r

Full-time

DFT Engineer - Post-Silicon Validation & Pattern Debug (Siemens Tools)

San Francisco, California

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Today

Own post-silicon structural test pattern debug and regeneration, including ATPG, MBIST, Boundary Scan, and related DFT flows Analyze pattern failures on silicon and drive corrective actions in collaboration with tester teams Utilize Siemens DFT/ATPG tools to modify, validate, and re-release production-ready test patterns Correlate tester results with design intent to isolate coverage gaps and failure mechanisms Drive closure of post-silicon DFT issues to improve yield and test robustness

Full-time

Electrical Engineer - Design for Test (DFT) & Automation Engineer

Scottsdale, Arizona

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Today

Basic Qualifications Requires a Bachelor's degree in Electrical Engineering, or a related Science, Engineering or Mathematics field. Also requires one year of experience, or a Master's degree. CLEARANCE REQUIREMENTS:: [Department of Defense Secret security clearance is preferred at time of hire.] Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within

Full-time

USD 85,807.00 - 95,193.00 per year

Principal Engineer - Design For Test (DFT)

Morrisville, North Carolina

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Today

Full-time

USD 160,400.00 - 237,320.00 per year

Lead Software Engineer, DFT/ATPG

Austin, Texas

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated engineer to work with the Modus Test R&D team working on Design For Test (DFT) and Automatic Test Pattern Generation (ATPG) Software. What You'll Be Doing Work as a team to build reliable, scalable and high performance software that are easy to use by engineers worldwideDevelop software tools in C/C++ to support DFT/ATPGResearch

Full-time

Principal DFT Engineer (Silicon Engineering)

Sunnyvale, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 210,000.00 - 295,000.00 per year

DFT - Tessent SSN

Remote

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13d ago

12+ month contractRemote/3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.

Easy Apply

Contract

60 - 90

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