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Job Title: Senior Physical Design Signoff Engineer (Top-Level SoC) Location: SanJose CA Contract Experience: 8+ Years Job Summary We are hiring experienced Physical Design Signoff Engineers for advanced-node SoC projects (7nm/5nm/3nm). Candidates should have strong expertise in full-chip signoff with multiple successful tapeouts and the ability to drive signoff-to-tapeout closure independently. Key Responsibilities Lead top-level signoff activities for high-performance SoCs.Collaborate with RTL
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